441 research outputs found
Standardization of Spirometry - 1987 Update
journal articleBiomedical Informatic
Testing Spirometers -ATS Standards
journal articleBiomedical Informatic
Standardization of Spirometry with Special Emphasis Field Testing
book chapterBiomedical Informatic
Standardization of Spirometry - 1987 Update
journal articleBiomedical Informatic
Standardization of Spirometry - 1987 Update
journal articleBiomedical Informatic
Evaluating Commercially Available Spirometers
journal articleBiomedical Informatic
Technology Development Standardization and Evaluation in Pulmonary Medicine
book chapterBiomedical Informatic
Controlled epitaxial graphene growth within amorphous carbon corrals
Structured growth of high quality graphene is necessary for technological
development of carbon based electronics. Specifically, control of the bunching
and placement of surface steps under epitaxial graphene on SiC is an important
consideration for graphene device production. We demonstrate lithographically
patterned evaporated amorphous carbon corrals as a method to pin SiC surface
steps. Evaporated amorphous carbon is an ideal step-flow barrier on SiC due to
its chemical compatibility with graphene growth and its structural stability at
high temperatures, as well as its patternability. The amorphous carbon is
deposited in vacuum on SiC prior to graphene growth. In the graphene furnace at
temperatures above 1200C, mobile SiC steps accumulate at these
amorphous carbon barriers, forming an aligned step free region for graphene
growth at temperatures above 1330C. AFM imaging and Raman spectroscopy
support the formation of quality step-free graphene sheets grown on SiC with
the step morphology aligned to the carbon grid
Wafer bonding solution to epitaxial graphene - silicon integration
The development of graphene electronics requires the integration of graphene
devices with Si-CMOS technology. Most strategies involve the transfer of
graphene sheets onto silicon, with the inherent difficulties of clean transfer
and subsequent graphene nano-patterning that degrades considerably the
electronic mobility of nanopatterned graphene. Epitaxial graphene (EG) by
contrast is grown on an essentially perfect crystalline (semi-insulating)
surface, and graphene nanostructures with exceptional properties have been
realized by a selective growth process on tailored SiC surface that requires no
graphene patterning. However, the temperatures required in this structured
growth process are too high for silicon technology. Here we demonstrate a new
graphene to Si integration strategy, with a bonded and interconnected compact
double-wafer structure. Using silicon-on-insulator technology (SOI) a thin
monocrystalline silicon layer ready for CMOS processing is applied on top of
epitaxial graphene on SiC. The parallel Si and graphene platforms are
interconnected by metal vias. This method inspired by the industrial
development of 3d hyper-integration stacking thin-film electronic devices
preserves the advantages of epitaxial graphene and enables the full spectrum of
CMOS processing.Comment: 15 pages, 7 figure
- …