Implementation of a Primary Tapped Transformer in a High Frequency Isolated Power Converter

Abstract: On load, transformer primary tap changing is not common in high frequency converters. This paper investigates a new converter topology to drive primary tapped transformers. The ideas that have been introduced previously are simply implemented into existing converter topologies which have been modified to accommodate a primary tapped transformer. The effects of efficiency with variation of source voltage and duty cycle are studied. It is shown that this topology can maintain a load voltage for a much wider source voltage variation without major sacrifices in efficiency

Some considerations for miniaturized measurement shunts in high frequency power electronic converters.

Abstract: Power semi-conductors are able to achieve switching transients within a few nanoseconds and possibly even faster. These fast switching transients will need to be measured and analyzed thoroughly. In this paper four different types of shunt constructions and installations are tested on the same power electronics circuit, giving widely diverse results. Interpreting and analyzing these measurement results will assist in developing accurate current measurement devices for fast switching transient power electronic converters of the future

An experimental study of switching GaN FETs in a coaxial transmission line

Abstract: The switching characteristics of GaN FETs have not yet been measured accurately because of their small electromagnetic size in relation to the circuit and the electromagnetic environment the measurements are exposed to. Switching GaN FETs in a transmission line will allow for measurements to be taken in an electromagnetically defined environment. The transmission line is adapted to take optimum measurements. This is proven by the waveforms presented

CheriRTOS: A Capability Model for Embedded Devices

Embedded systems are deployed ubiquitously among various sectors including automotive, medical, robotics and avionics. As these devices become increasingly connected, the attack surface also increases tremendously; new mechanisms must be deployed to defend against more sophisticated attacks while not violating resource constraints. In this paper we present CheriRTOS on CHERI-64, a hardware-software platform atop Capability Hardware Enhanced RISC Instructions (CHERI) for embedded systems. Our system provides efficient and scalable task isolation, fast and secure inter-task communication, fine-grained memory safety, and real-time guarantees, using hardware capabilities as the sole protection mechanism. We summarize state-of-the-art se- curity and memory safety for embedded systems for comparison with our platform, illustrating the superior substrate provided by CHERI’s capabilities. Finally, our evaluations show that a capability system can be implemented within the constraints of embedded systems