New Planar P-time Computable Six-Vertex Models and a Complete Complexity Classification

We discover new P-time computable six-vertex models on planar graphs beyond Kasteleyn's algorithm for counting planar perfect matchings. We further prove that there are no more: Together, they exhaust all P-time computable six-vertex models on planar graphs, assuming #P is not P. This leads to the following exact complexity classification: For every parameter setting in ${\mathbb C}$ for the six-vertex model, the partition function is either (1) computable in P-time for every graph, or (2) #P-hard for general graphs but computable in P-time for planar graphs, or (3) #P-hard even for planar graphs. The classification has an explicit criterion. The new P-time cases in (2) provably cannot be subsumed by Kasteleyn's algorithm. They are obtained by a non-local connection to #CSP, defined in terms of a "loop space". This is the first substantive advance toward a planar Holant classification with not necessarily symmetric constraints. We introduce M\"obius transformation on ${\mathbb C}$ as a powerful new tool in hardness proofs for counting problems.Comment: 61 pages, 16 figures. An extended abstract appears in SODA 202

Constructing conducted emission models for integrated circuits

Conducted emissions, noise conducted out of integrated circuit pins, play an important role in determining the system level EMC performance. Characterizing conducted emissions from ICs is investigated and the corresponding noise models are developed in this thesis. Both simulation IBIS and measurement based methods for noise-model construction are studied. The constructed noise source model for a test IC is applied in system-level simulations and the calculated far field radiation is validated with measurements. The agreement in the simulated and measured results demonstrates the effectiveness of the constructed model for characterizing the conducted emissions from an IC I/O pin --Abstract, page iii

Modal based BGA modeling in high-speed package

In the Section 1, the improved Root-Omega method for extracting dielectric properties from fabricated multilayer printed circuit boards is proposed. Based on the electrical properties of fabricated transmission lines, the improved Root-Omega method applied to cases with smooth and rough conductors is validated using simulations. Error sensitivity analysis is performed to demonstrate the potential errors in the original Root-Omega procedure and the error sensitivity is significantly reduced by the proposed improvements. In the Section 2, a fast modal-based approach is developed to accurately and efficiently capture the proximity effect. Image theory is also applied in the proposed approach to reduce the computational domain from 3D structure to 2D. The matrix reduction approach is applied to obtain the physical loop inductance. The lumped capacitance is obtained. A π topology equivalent circuit model for the BGA structure is built. Good agreement between the equivalent circuit model and full wave simulation can be achieved up to 40GHz. In the Section 3, the proximity effect for BGAs between parallel plates is carefully considered. A modal-based cavity method is proposed to extract the partial inductance of two parallel plates. The modal basis function is used to count for the non-uniformly distributed current density. The physical loop inductance is further obtained from the matrix reduction approach. The extracted physical loop inductance is validated with a commercial finite element method-based tool. The boundary effect is demonstrated in the inductance extraction. The proposed method is used to optimize for the power distributed network design --Abstract, page iii