33 research outputs found

    Noncoding variation of the gene for ferritin light chain in hereditary and age-related cataract

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    PURPOSE: Cataract is a clinically and genetically heterogeneous disorder of the ocular lens and an important cause of visual impairment. The aim of this study was to map and identify the gene underlying autosomal dominant cataract segregating in a four-generation family, determine the lens expression profile of the identified gene, and test for its association with age-related cataract in a case-control cohort. METHODS: Genomic DNA was prepared from blood leukocytes, and genotyping was performed by means of single-nucleotide polymorphism markers and microsatellite markers. Linkage analyses were performed using the GeneHunter and MLINK programs, and mutation detection was achieved by dideoxy cycle sequencing. Lens expression studies were performed using reverse-transcription polymerase chain reaction (RT–PCR) and in situ hybridization. RESULTS: Genome-wide linkage analysis with single nucleotide polymorphism markers in the family identified a likely disease-haplotype interval on chromosome 19q (rs888861-[~17Mb]-rs8111640) that encompassed the microsatellite marker D19S879 (logarithm of the odds score [Z]=2.03, recombination distance [θ]=0). Mutation profiling of positional-candidate genes detected a heterozygous, noncoding G-to-T transversion (c.-168G>T) located in the iron response element (IRE) of the gene coding for ferritin light chain (FTL) that cosegregated with cataract in the family. Serum ferritin levels were found to be abnormally elevated (~fourfold), without evidence of iron overload, in an affected family member; this was consistent with a diagnosis of hereditary hyperferritinemia-cataract syndrome. No sequence variations located within the IRE were detected in a cohort of 197 cases with age-related cataract and 102 controls with clear lenses. Expression studies of human FTL, and its mouse counterpart FTL1, in the lens detected RT–PCR amplicons containing full-length protein-coding regions, and strong in situ localization of FTL1 transcripts to the lens equatorial epithelium and peripheral cortex. CONCLUSIONS: The data are consistent with robust transcription of FTL in the lens, and suggest that whereas variations clustered in the IRE of the FTL gene are directly associated with hereditary hyperferritinemia-cataract syndrome, such IRE variations are unlikely to play a significant role in the genetic etiology of age-related cataract

    Class D amplifier with pseudo-randomized carrier frequency modulation (PRCFM) for EMI mitigation

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    Class D amplifiers are found in nearly all portable electronic products for their small size and power efficiency. Due to their high frequency switching operation, they generate significant amount of electromagnetic interference (EMI) and usually off-chip filters are necessary in order for them to comply with the international regulatory EMI limits. With the continuous trend of product miniaturization, filter-less Class D amplifiers are gaining attention recently. Without the off-chip filter, designing a fully integrated filter-less Class D amplifier to meet the EMI requirements can be challenging. This thesis develops and implements a pseudo-randomized carrier frequency modulation (PRCFM) technique in both analog and digital filterless Class D audio power amplifiers for EMI mitigation purposes so that these amplifiers fulfill the electromagnetic compatibility (EMC) requirement without the needs of off-chip filters. The PRCFM circuit is implemented with a frequency divider and a linear feedback shift register (LFSR). The proposed amplifier also features a peak detector to improve the power conversion efficiency when it operates under low audio input condition. An analog filter-less Class D amplifier is designed and fabricated using 0.18 µm CMOS process technology with a size of 1 mm2 and the proposed PRCFM circuit occupies only less than 1% of the total chip area. The effectiveness of the PRCFM scheme for EMI mitigation is demonstrated experimentally. The PRCFM circuit consumes very little additional power and therefore has little impact on the power efficiency of the amplifier. In addition, the amplifier still maintains excellent total harmonic distortion (THD) over the audio band of interest (100 Hz - 6 kHz) and the typical modulation index range. With the encouraging results, the PRCFM technique is further extended to a digital Class D amplifier and similar EMI mitigation performance has also been demonstrated. The digital Class D amplifier consists of a digital pulse width modulation (DPWM) circuit, a power stage, a PRCFM circuit and a low pass filter (LPF). Moreover, an efficient algorithmic sampling process and a hybrid pulse generation method are proposed to improve THD performance. The circuit is first simulated in Matlab Simulink and then implemented with field-programmable gate array (FPGA). Both simulated and measured results have shown that the PRCFM spreads the switching frequency of the Class D amplifier from 145 kHz to 295 kHz in 31 frequency steps using a pseudo-random (PR) pattern, which results in EMI reduction of 7.4 dB, with acceptable THD.DOCTOR OF PHILOSOPHY (EEE

    Low power integrated circuit design with stacking technique

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    Driven by the battery-operated applications in portable devices, circuit design techniques for reducing the power consumption have been extensively investigated in the past decade. One common approach is the supply voltage scaling, where different voltages are generated by DC-DC converters and provided to corresponding low supply circuits. Because each circuit is supplied by the lowest possible voltage, the power consumption is greatly reduced. However, the voltage converters employed in this method bring in extra design cost and power consumption. Therefore in this paper, the voltage converter is removed from conventional design and the possibility of stacking multiple low supply circuits to achieve virtual supply voltage scaling is discussed. The proposed technique connects the stacking circuits directly to the high voltage source. It saves one or more voltage converters, therefore reduces the chip area and eliminates the power loss associated with the converters. The proposed stacking structure is more applicable to systems with single high voltage supply
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