Clock Gating Assertion Check An Approach Towards Efficient Verification Closure On Clock Gating Functionality

One of the power reduction techniques widely used in Register Transfer Level (RTL) stage of a design is clock gating. However, the addition of clock gating logics has increased the complexity of a design and therefore considerable amount of verification effort is required. The conventional verification method used widely is the scoreboard checking mechanism in Open Verification Methodology (OVM) verification environment. In addition, there are several methods proposed over the years to solve the verification of clock gating logics, for example, same master seed usage in multiple simulations, RTL to ACL2 translation and gated clock timing verification. However, the previous proposed methods still lack the capability to completely comprehend the checking of the correctness of clock gating logics of a design. The proposed verification method, called Clock Gating Assertion Check (CGAC) is aimed at addressing the limitation of the conventional verification method. The method is independent of verification environment used in a test bench. Besides, the proposed method is also aiming at achieving an efficient pre-silicon verification closure on clock gating logics with minimum verification effort. The proposed method is an automated flow that takes in two main inputs, namely codes written in Hardware Description Language (HDL) in RTL stage and clock domains information of a design. By using the main inputs, the proposed method generates assertion checks at possible clock gating boundary conditions. The clock gating logics of two Soft Intellectual Property (SIP) designs were verified using the CGAC method. The details of the implementation of the method are discussed in this thesis. By using the method, a total of five clock gating bugs were found and analysis on the impacts of the bugs is discussed. The proposed method further improved the efficiency of clock gating functional verification by 87.5% and 75% in terms of verification time spent in weeks for the first and second design respectively compared to the conventional method used which is OVM. However, there are a few limitations in the proposed method whereby it is used within Intel, the design information cannot be disclosed in this thesis and the designs are not within the author’s control. As a conclusion, based on the results obtained, it is concluded that the proposed method is proven effective in ensuring the correct clock gating implementation in a design

The Fidelity of Measurement-Based Quantum Computation under a Boson Environment

We investigate the fidelity of the measurement-based quantum computation (MBQC) when it is coupled with boson environment, by measuring cluster state fidelity and gate fidelity. Two different schemes of cluster state preparation are studied. In the Controlled-Z (CZ) creation scheme, cluster states are prepared by entangling all qubits in $|+\rangle$ state with CZ gates on all neighboring sites. The fidelity shows an oscillation pattern over time evolution. The influence of environment temperature is evaluated, and suggestions are given to enhance the performance of MBQC realized in this way. In the Hamiltonian creation scheme, cluster states are made by cooling a system with cluster Hamiltonians, of which ground states are cluster states. The fidelity sudden drop phenomenon is discovered. When the coupling is below a threshold, MBQC systems are highly robust against the noise. Our main environment model is the one with a single collective bosonic mode.Comment: 13 pages, 16 figure

Coherent Single Spin Source based on topological insulator

We report on the injection of quantized pure spin current into quantum conductors. In particular, we propose an on demand single spin source generated by periodically varying the gate voltages of two quantum dots that are connected to a two dimensional topological insulator via tunneling barriers. Due to the nature of the helical states of the topological insulator, one or several {\it spin pair}s can be pumped out per cycle giving rise to a pure quantized alternating spin current. Depending on the phase difference between two gate voltages, this device can serve as an on demand single spin emitter or single charge emitter. Again due to the helicity of the topological insulator, the single spin emitter or charge emitter is dissipationless and immune to disorders. The proposed single spin emitter can be an important building block of future spintronic devices.Comment: 5 pages, 4 figures, append one co-author that has been misse