Producing Random Bits with Delay-Line Based Ring Oscillators

One of the sources of randomness for a random bit generator (RBG) is jitter present in rectangular signals produced by ring oscillators (ROs). This paper presents a novel approach for the design of delays used in these oscillators. We suggest using delay elements made on carry4 primitives instead of series of inverters or latches considered in the literature. It enables the construction of many high frequency ring oscillators with different nominal frequencies in the same field programmable gate array (FPGA). To assess the unpredictability of bits produced by RO-based RBG, the restarts mechanism, proposed in earlier papers, was used. The output sequences pass all NIST 800-22 statistical tests for smaller number of ring oscillators than the constructions described in the literature. Due to the number of ROs with different nominal frequencies and the method of construction of carry4 primitives, it is expected that the proposed RBG is more robust to cryptographic attacks than RBGs using inverters or latches as delay element

A Random Number Generator Using Ring Oscillators and SHA-256 as Post-Processing

Today, cryptographic security depends primarily on having strong keys and keeping them secret. The keys should be produced by a reliable and robust to external manipulations generators of random numbers. To hamper different attacks, the generators should be implemented in the same chip as a cryptographic system using random numbers. It forces a designer to create a random number generator purely digitally. Unfortunately, the obtained sequences are biased and do not pass many statistical tests. Therefore an output of the random number generator has to be subjected to a transformation called post-processing. In this paper the hash function SHA-256 as post-processing of bits produced by a combined random bit generator using jitter observed in ring oscillators (ROs) is proposed. All components – the random number generator and the SHA-256, are implemented in a single Field Programmable Gate Array (FPGA). We expect that the proposed solution, implemented in the same FPGA together with a cryptographic system, is more attack-resistant owing to many sources of randomness with significantly different nominal frequencies

Computationally Efficient Wideband Spectrum Sensing through Cumulative Distribution Function and Machine Learning

Blind spectrum sensing (BSS) is crucial for identifying unknown signals in scenarios with limited prior knowledge. Traditional methods face challenges with unknown and timevarying signals, especially in the presence of noise interference. This paper addresses these issues by introducing a statistical signal processing framework that extends the use of machine learning (ML) features. Our approach improves BSS by incorporating cumulative distribution functions (CDFs) into unsupervised ML, enabling effective clustering of diverse transmission states without assumptions about specific noise distributions. Additionally, we introduce a temporal decomposition technique using shorter Fast Fourier Transforms (FFTs), enhancing the learning process, reducing system inertia, and minimizing data requirements for retraining under dynamic conditions. We evaluate our method, focusing on various features/approaches for incorporating CDFs into ML, including centroid, linear approximation, and low-order statistics. Simulation results demonstrate robust detection in a standard transmission scenario with a Gaussian pulse amidst additive white Gaussian noise, maintaining a consistently low false alarm rate. These findings highlight our BSS approach’s effectiveness and practical potential in handling unknown signals in challenging environments. This research provides valuable insights, laying the groundwork for practical implementation in real-world scenarios