Damage-Free Smooth-Sidewall InGaAs Nanopillar Array by Metal-Assisted Chemical Etching

Producing densely packed high aspect ratio In_0.53Ga_0.47As nanostructures without surface damage is critical for beyond Si-CMOS nanoelectronic and optoelectronic devices. However, conventional dry etching methods are known to produce irreversible damage to III−V compound semiconductors because of the inherent high-energy ion-driven process. In this work, we demonstrate the realization of ordered, uniform, array-based In_0.53Ga_0.47As pillars with diameters as small as 200 nm using the damage-free metal-assisted chemical etching (MacEtch) technology combined with the post-MacEtch digital etching smoothing. The etching mechanism of In<i>_x</i>Ga_1−<i>x</i>As is explored through the characterization of pillar morphology and porosity as a function of etching condition and indium composition. The etching behavior of In_0.53Ga_0.47As, in contrast to higher bandgap semiconductors (<i>e</i>.<i>g</i>., Si or GaAs), can be interpreted by a Schottky barrier height model that dictates the etching mechanism constantly in the mass transport limited regime because of the low barrier height. A broader impact of this work relates to the complete elimination of surface roughness or porosity related defects, which can be prevalent byproducts of MacEtch, by post-MacEtch digital etching. Side-by-side comparison of the midgap interface state density and flat-band capacitance hysteresis of both the unprocessed planar and MacEtched pillar In_0.53Ga_0.47As metal-oxide-semiconductor capacitors further confirms that the surface of the resultant pillars is as smooth and defect-free as before etching. MacEtch combined with digital etching offers a simple, room-temperature, and low-cost method for the formation of high-quality In_0.53Ga_0.47As nanostructures that will potentially enable large-volume production of In_0.53Ga_0.47As-based devices including three-dimensional transistors and high-efficiency infrared photodetectors

Self-Anchored Catalyst Interface Enables Ordered Via Array Formation from Submicrometer to Millimeter Scale for Polycrystalline and Single-Crystalline Silicon

Defying text definitions of wet etching, metal-assisted chemical etching (MacEtch), a solution-based, damage-free semiconductor etching method, is directional, where the metal catalyst film sinks with the semiconductor etching front, producing 3D semiconductor structures that are complementary to the metal catalyst film pattern. The same recipe that works perfectly to produce ordered array of nanostructures for single-crystalline Si (c-Si) fails completely when applied to polycrystalline Si (poly-Si) with the same doping type and level. Another long-standing challenge for MacEtch is the difficulty of uniformly etching across feature sizes larger than a few micrometers because of the nature of lateral etching. The issue of interface control between the catalyst and the semiconductor in both lateral and vertical directions over time and over distance needs to be systematically addressed. Here, we present a self-anchored catalyst (SAC) MacEtch method, where a nanoporous catalyst film is used to produce nanowires through the pinholes, which in turn physically anchor the catalyst film from detouring as it descends. The systematic vertical etch rate study as a function of porous catalyst diameter from 200 to 900 nm shows that the SAC-MacEtch not only confines the etching direction but also enhances the etch rate due to the increased liquid access path, significantly delaying the onset of the mass-transport-limited critical diameter compared to nonporous catalyst c-Si counterpart. With this enhanced mass transport approach, vias on multistacks of poly-Si/SiO₂ are also formed with excellent vertical registry through the polystack, even though they are separated by SiO₂ which is readily removed by HF alone with no anisotropy. In addition, 320 μm square through-Si-via (TSV) arrays in 550 μm thick c-Si are realized. The ability of SAC-MacEtch to etch through poly/oxide/poly stack as well as more than half millimeter thick silicon with excellent site specificity for a wide range of feature sizes has significant implications for 2.5D/3D photonic and electronic device applications

Enhanced Performance of Ge Photodiodes <i>via</i> Monolithic Antireflection Texturing and α‑Ge Self-Passivation by Inverse Metal-Assisted Chemical Etching

Surface antireflection micro and nanostructures, normally formed by conventional reactive ion etching, offer advantages in photovoltaic and optoelectronic applications, including wider spectral wavelength ranges and acceptance angles. One challenge in incorporating these structures into devices is that optimal optical properties do not always translate into electrical performance due to surface damage, which significantly increases surface recombination. Here, we present a simple approach for fabricating antireflection structures, with self-passivated amorphous Ge (α-Ge) surfaces, on single crystalline Ge (c-Ge) surface using the inverse metal-assisted chemical etching technology (I-MacEtch). Vertical Schottky Ge photodiodes fabricated with surface structures involving arrays of pyramids or periodic nano-indentations show clear improvements not only in responsivity, due to enhanced optical absorption, but also in dark current. The dark current reduction is attributed to the Schottky barrier height increase and self-passivation effect of the i-MacEtch induced α-Ge layer formed on top of the c-Ge surface. The results demonstrated in this work show that MacEtch can be a viable technology for advanced light trapping and surface engineering in Ge and other semiconductor based optoelectronic devices

Direct Electrical Probing of Periodic Modulation of Zinc-Dopant Distributions in Planar Gallium Arsenide Nanowires

Selective lateral epitaxial (SLE) semiconductor nanowires (NWs), with their perfect in-plane epitaxial alignment, ability to form lateral complex p–n junctions <i>in situ</i>, and compatibility with planar processing, are a distinctive platform for next-generation device development. However, the incorporation and distribution of impurity dopants in these planar NWs <i>via</i> the vapor−liquid−solid growth mechanism remain relatively unexplored. Here, we present a detailed study of SLE planar GaAs NWs containing multiple alternating axial segments doped with Si and Zn impurities by metalorganic chemical vapor deposition. The dopant profile of the lateral multi-p–n junction GaAs NWs was imaged simultaneously with nanowire topography using scanning microwave impedance microscopy and correlated with infrared scattering-type near-field optical microscopy. Our results provide unambiguous evidence that Zn dopants in the periodically twinned and topologically corrugated p-type segments are preferentially segregated at twin plane boundaries, while Si impurity atoms are uniformly distributed within the n-type segments of the NWs. These results are further supported by microwave impedance modulation microscopy. The density functional theory based modeling shows that the presence of Zn dopant atoms reduces the formation energy of these twin planes, and the effect becomes significantly stronger with a slight increase of Zn concentration. This implies that the twin formation is expected to appear when a threshold planar concentration of Zn is achieved, making the onset and twin periodicity dependent on both Zn concentration and nanowire diameter, in perfect agreement with our experimental observations