Energy-Efficient Digital Signal Processing Hardware Design.

As CMOS technology has developed considerably in the last few decades, many SoCs have been implemented across different application areas due to reduced area and power consumption. Digital signal processing (DSP) algorithms are frequently employed in these systems to achieve more accurate operation or faster computation. However, CMOS technology scaling started to slow down recently and relatively large systems consume too much power to rely only on the scaling effect while system power budget such as battery capacity improves slowly. In addition, there exist increasing needs for miniaturized computing systems including sensor nodes that can accomplish similar operations with significantly smaller power budget. Voltage scaling is one of the most promising power saving techniques due to quadratic switching power reduction effect, making it necessary feature for even high-end processors. However, in order to achieve maximum possible energy efficiency, systems should operate in near or sub-threshold regimes where leakage takes significant portion of power. In this dissertation, a few key energy-aware design approaches are described. Considering prominent leakage and larger PVT variability in low operating voltages, multi-level energy saving techniques to be described are applied to key building blocks in DSP applications: architecture study, algorithm-architecture co-optimization, and robust yet low-power memory design. Finally, described approaches are applied to design examples including a visual navigation accelerator, ultra-low power biomedical SoC and face detection/recognition processor, resulting in 2~100 times power savings than state-of-the-art.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/110496/1/djeon_1.pd

A 0.6V, 8mW 3D Vision Processor for a Navigation Device for the Visually Impaired

This paper presents an energy-efficient computer vision processor for a navigation device for the visually impaired. Utilizing a shared parallel datapath, out-of-order processing and co-optimization with hardware-oriented algorithms, the processor consumes 8mW at 0.6V while processing 30 fps input data stream in real time. The test chip fabricated in 40nm is demonstrated as a core part of a navigation device based on a ToF camera, which successfully detects safe areas and obstacles.Texas Instruments Incorporate

Pipeline strategy for improving optimal energy efficiency in ultra-low voltage design

ABSTRACT This paper investigates pipelining methodologies for the ultra low voltage regime. Based on an analytical model and simulations, we propose a pipelining technique that provides higher energy efficiency and performance than conventional approaches to ultra low voltage design. Two-phase latch based design and sequential circuit optimizations are also proposed to further improve energy efficiency and performance. Silicon results demonstrate a 16b multiplier using the approaches in 65nm CMOS improve energy efficiency by 30% and performance by 60%

An area-efficient 128-channel spike sorting processor for real-time neural recording with 0.175 μ W/channel in 65-nm CMOS

This paper presents a power- and area-efficient spike sorting processor (SSP) for real-time neural recordings. The proposed SSP includes novel detection, feature extraction, and improved K-means algorithms for better clustering accuracy, online clustering performance, and lower power and smaller area per channel. Time-multiplexed registers are utilized in the detector for dynamic power reduction. Finally, an ultralow-voltage 8T static random access memory (SRAM) is developed to reduce area and leakage consumption when compared to D flip-flop -based memory. The proposed SSP, fabricated in 65-nm CMOS process technology, consumes only 0.175 μW/channel when processing 128 input channels at 3.2 MHz and 0.54 V, which is the lowest among the compared state-of-the-art SSPs. The proposed SSP also occupies 0.003 mm2/channel, which allows 333 channels/mm2

Vertical Metal-Oxide Electrochemical Memory for High-Density Synaptic Array Based High-Performance Neuromorphic Computing

Cross-point arrays of analog synaptic devices are expected to realize neuromorphic computing hardware for neural network computations with compelling speed boost and superior energy efficiency, as opposed to the conventional hardware based on the von Neumann architecture. To achieve desired characteristics of analog synaptic devices for fully parallel vector-matrix multiplication and vector-vector outer-product updates, metal-oxide based electrochemical random-access memory (ECRAM) is proposed as a promising synaptic device due to its complementary metal-oxide-semiconductor-compatibility and outstanding synaptic characteristics over other non-volatile memory candidates. In this work, ECRAM devices with 3D vertical structure is fabricated to demonstrate a minimal 4F(2) cell size, highly scalable channel volume and low programming energy, providing optimized synaptic device performance and characteristics as well as high integrity as a cross-point array. Various weight-update profiles of the vertical ECRAM devices are obtained by adjusting programming voltage pulses, exhibiting trade-offs among dynamic range, linearity, symmetry, and update deviation. Based on simulation with advanced algorithms for analog cross-point array and neural network designs, the potential of vertical ECRAM for high-density array is evaluated. Simulation studies suggest that the neuromorphic computing performance can be improved further by balancing the weight update characteristics of vertical ECRAM.N

Extremely Stable Luminescent Crosslinked Perovskite Nanoparticles under Harsh Environments over 1.5 Years

© 2020 Wiley-VCH GmbHOrganic–inorganic hybrid perovskite nanoparticles (NPs) are a very strong candidate emitter that can meet the high luminescence efficiency and high color standard of Rec.2020. However, the instability of perovskite NPs is the most critical unsolved problem that limits their practical application. Here, an extremely stable crosslinked perovskite NP (CPN) is reported that maintains high photoluminescence quantum yield for 1.5 years (>600 d) in air and in harsher liquid environments (e.g., in water, acid, or base solutions, and in various polar solvents), and for more than 100 d under 85 °C and 85% relative humidity without additional encapsulation. Unsaturated hydrocarbons in both the acid and base ligands of NPs are chemically crosslinked with a methacrylate-functionalized matrix, which prevents decomposition of the perovskite crystals. Counterintuitively, water vapor permeating through the crosslinked matrix chemically passivates surface defects in the NPs and reduces nonradiative recombination. Green-emitting and white-emitting flexible large-area displays are demonstrated, which are stable for >400 d in air and in water. The high stability of the CPN in water enables biocompatible cell proliferation which is usually impossible when toxic Pb elements are present. The stable materials design strategies provide a breakthrough toward commercialization of perovskite NPs in displays and bio-related applications.