15 research outputs found

    Performance of a low data rate speech codec for land-mobile satellite communications

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    In an effort to foster the development of new technologies for the emerging land mobile satellite communications services, JPL funded two development contracts in 1984: one to the Univ. of Calif., Santa Barbara and the other to the Georgia Inst. of Technology, to develop algorithms and real time hardware for near toll quality speech compression at 4800 bits per second. Both universities have developed and delivered speech codecs to JPL, and the UCSB codec was extensively tested by JPL in a variety of experimental setups. The basic UCSB speech codec algorithms and the test results of the various experiments performed with this codec are presented

    An 8-DPSK TCM modem for MSAT-X

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    This paper describes the real-time digital implementation of an 8-differentiated phase-shift keying (DPSK) trellis-coded modulation (TCM) modem for operation on an L-band, 5 kHz wide, land mobile satellite (LMS) channel. The modem architecture as well as some of the signal processing techniques employed in the modem to combat the LMS channel impairments are described, and the modem performance over the fading channel is presented

    Field trials of a NASA-developed mobile satellite terminal

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    Various field trials have been performed to validate and optimize the technologies developed by the Mobile Satellite Experiment (MSAT-X). For each of the field experiments performed, a brief description of the experiment is provided, followed by a summary of the experimental results. Emphasis is placed on the two full scale land mobile and aeronautical mobile experiments. Experiments planned for the near future are also presented

    ACTS broadband aeronautical experiment

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    In the last decade, the demand for reliable data, voice, and video satellite communication links between aircraft and ground to improve air traffic control, airline management, and to meet the growing demand for passenger communications has increased significantly. It is expected that in the near future, the spectrum required for aeronautical communication services will grow significantly beyond that currently available at L-band. In anticipation of this, JPL is developing an experimental broadband aeronautical satellite communications system that will utilize NASA's Advanced Communications Technology Satellite (ACTS) as a satellite of opportunity and the technology developed under JPL's ACTS Mobile Terminal (AMT) Task to evaluate the feasibility of using K/Ka-band for these applications. The application of K/Ka-band for aeronautical satellite communications at cruise altitudes is particularly promising for several reasons: (1) the minimal amount of signal attenuation due to rain; (2) the reduced drag due to the smaller K/Ka-band antennas (as compared to the current L-band systems); and (3) the large amount of available bandwidth. The increased bandwidth available at these frequencies is expected to lead to significantly improved passenger communications - including full-duplex compressed video and multiple channel voice. A description of the proposed broadband experimental system will be presented including: (1) applications of K/Ka-band aeronautical satellite technology to U.S. industry; (2) the experiment objectives; (3) the experiment set-up; (4) experimental equipment description; and (5) industrial participation in the experiment and the benefits

    CoNNeCT Baseband Processor Module

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    A document describes the CoNNeCT Baseband Processor Module (BPM) based on an updated processor, memory technology, and field-programmable gate arrays (FPGAs). The BPM was developed from a requirement to provide sufficient computing power and memory storage to conduct experiments for a Software Defined Radio (SDR) to be implemented. The flight SDR uses the AT697 SPARC processor with on-chip data and instruction cache. The non-volatile memory has been increased from a 20-Mbit EEPROM (electrically erasable programmable read only memory) to a 4-Gbit Flash, managed by the RTAX2000 Housekeeper, allowing more programs and FPGA bit-files to be stored. The volatile memory has been increased from a 20-Mbit SRAM (static random access memory) to a 1.25-Gbit SDRAM (synchronous dynamic random access memory), providing additional memory space for more complex operating systems and programs to be executed on the SPARC. All memory is EDAC (error detection and correction) protected, while the SPARC processor implements fault protection via TMR (triple modular redundancy) architecture. Further capability over prior BPM designs includes the addition of a second FPGA to implement features beyond the resources of a single FPGA. Both FPGAs are implemented with Xilinx Virtex-II and are interconnected by a 96-bit bus to facilitate data exchange. Dedicated 1.25- Gbit SDRAMs are wired to each Xilinx FPGA to accommodate high rate data buffering for SDR applications as well as independent SpaceWire interfaces. The RTAX2000 manages scrub and configuration of each Xilinx
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