Advanced materials nanocharacterization

This special issue of Nanoscale Research Letters contains scientific contributions presented at the Symposium D "Multidimensional Electrical and Chemical Characterization at the Nanometer-scale of Organic and Inorganic Semiconductors" of the E-MRS Fall Meeting 2010, which was held in Warsaw, Poland from 13th to 17th September, 2010

Multiscale investigation of graphene layers on 6H-SiC(000-1)

In this article, a multiscale investigation of few graphene layers grown on 6H-SiC(000-1) under ultrahigh vacuum (UHV) conditions is presented. At 100-μm scale, the authors show that the UHV growth yields few layer graphene (FLG) with an average thickness given by Auger spectroscopy between 1 and 2 graphene planes. At the same scale, electron diffraction reveals a significant rotational disorder between the first graphene layer and the SiC surface, although well-defined preferred orientations exist. This is confirmed at the nanometer scale by scanning tunneling microscopy (STM). Finally, STM (at the nm scale) and Raman spectroscopy (at the μm scale) show that the FLG stacking is turbostratic, and that the domain size of the crystallites ranges from 10 to 100 nm. The most striking result is that the FLGs experience a strong compressive stress that is seldom observed for graphene grown on the C face of SiC substrates

Multidimensional characterization, Landau levels and Density of States in epitaxial graphene grown on SiC substrates

Using high-temperature annealing conditions with a graphite cap covering the C-face of, both, on axis and 8° off-axis 4H-SiC samples, large and homogeneous single epitaxial graphene layers have been grown. Raman spectroscopy shows evidence of the almost free-standing character of these monolayer graphene sheets, which was confirmed by magneto-transport measurements. On the best samples, we find a moderate p-type doping, a high-carrier mobility and resolve the half-integer quantum Hall effect typical of high-quality graphene samples. A rough estimation of the density of states is given from temperature measurements

Current status of self-organized epitaxial graphene ribbons on the C face of 6H–SiC substrates

International audienceThe current status of long, self-organized, epitaxial graphene ribbons grown on the (000-1) face of 6H-SiC substrates is reviewed. First, starting from the early stage of growth it is shown that on the C-face of 6H-SiC substrates the sublimation process is not homogeneous. Most of the time it starts from defective sites, dislocations or point defects, that define nearly circular flakes surrounded by bare SiC. These flakes have a volcano-like shape with a graphite chimney at center, where the original defect was located. At higher temperature a complete conversion occurs, which is not yet homogeneous on the whole sample. This growth process can be modified by covering the sample with a graphite cap. It changes the physics of the surface reconstruction during the Si-sublimation process and, on the C-face, makes more efficient the reconstruction of few selected terraces with respect to the others. The net result is the formation of strongly step bunched areas with, in between, long and large reconstructed terraces covered by graphitic material. Despite the low intrinsic optical absorption of few graphene layers on SiC, micro-transmission experiments, complemented by micro-Raman spectroscopy, demonstrate that most of this graphitic coverage is made of one or two homogeneous graphene layers. We show also that most of the thermal stress between the graphene layer and the 6H-SiC substrate is relaxed by pleats or wrinkles which are clearly visible on the AFM images. Finally, the results of transport experiments performed on the graphitic ribbons reveal the p-type character of the ribbons

Micro-Raman and micro-transmission imaging of epitaxial graphene grown on the Si and C faces of 6H-SiC

Micro-Raman and micro-transmission imaging experiments have been done on epitaxial graphene grown on the C- and Si-faces of on-axis 6H-SiC substrates. On the C-face it is shown that the SiC sublimation process results in the growth of long and isolated graphene ribbons (up to 600 μm) that are strain-relaxed and lightly p-type doped. In this case, combining the results of micro-Raman spectroscopy with micro-transmission measurements, we were able to ascertain that uniform monolayer ribbons were grown and found also Bernal stacked and misoriented bilayer ribbons. On the Si-face, the situation is completely different. A full graphene coverage of the SiC surface is achieved but anisotropic growth still occurs, because of the step-bunched SiC surface reconstruction. While in the middle of reconstructed terraces thin graphene stacks (up to 5 layers) are grown, thicker graphene stripes appear at step edges. In both the cases, the strong interaction between the graphene layers and the underlying SiC substrate induces a high compressive thermal strain and n-type doping

Raman Imaging in Semiconductor Physics: Applications to Microelectronic Materials and Devices

International audienceThe unique versatility of micro-Raman spectroscopy (μRS) in semicon- ductor physics remains in Raman imaging. Numerous applications cover the whole development of modern electronic and optoelectronic devices: from semiconduc- tor growth to advanced device inspection tools. In this chapter, a wide variety of semiconductors (SiC, graphene, GaN, GaAs, SiGe, strained Si, sSOI, SGOI) and devices (FETs, lasers, MEMS) are addressed. First, it will be shown how Raman mapping enables to check the crystalline quality, the composition, the doping, and the uniformity of as-grown semiconductors. Then, we will focus on the most popular application in microelectronics: strain measurements either at the device or at the full wafer scale. Finally, we will show how μRS imaging can be used for final device inspection through the temperature mapping of operating devices (FETs, lasers, actuators)

Elaboration et caractérisation de composants type MOSFET en 4H-SiC orienté (11-20)

MONTPELLIER-BU Sciences (341722106) / SudocSudocFranceF

Intensity ratio of the doublet signature of excitons bound to 3C-SiC stacking faults in a 4H-SiC matrix

In 4H-SiC, 3C stacking fault (SF) behaves like a finite thickness type U quantum well. As a consequence, it can bind two excitons per well. We show in this work that, as the SF thickness increases, the relative intensity of the two transitions changes. This comes from a change in the wave functions overlap between the electron trapped in the well and the holes trapped neighbouring parts of the 4H-SiC matrix

Technologie d'oxydation pour la fabrication de composants MOSFETs en SiC

De nos jours, les dispositifs d'électroniques de puissance sont principalement basés sur la technologie silicium qui est mature et très bien établie. Toutefois, le silicium présente quelques limitations importantes concernant les pertes de puissance, le fonctionnement à haute température et la vitesse de commutation. Par ailleurs, la technologie silicium a presque atteint ses limites physiques. Ainsi, une nouvelle génération de dispositifs de puissance à base de nouveaux matériaux doit être développée pour faire face aux futurs défis énergiques. Aujourd'hui, le matériau semi-conducteur le plus prometteur est le carbure de silicium (SiC). SiC est considéré de plus en plus comme le meilleur candidat pour surmonter les limites intrinsèques du silicium pour l'élaboration de dispositifs de haute puissance et haute température. Il montre le meilleur compromis entre les caractéristiques théoriques et les réelles disponibilités commerciales de la matière première et de la maturité de ses procédés technologiques.Cette thèse est axée sur les dispositifs d'alimentation à base de SiC, en particulier, sur l'un des enjeux majeurs de la technologie SiC: le procédé d'oxydation. En effet, le SiC peut être facilement oxydé comme le silicium pour former une fine couche de dioxyde de silicium (SiO2). Ceci fournit une occasion unique de développer des dispositifs Métal-Oxyde-Semiconducteur (MOS), comme en technologie silicium. Malheureusement, la qualité de l'interface oxyde/SiC et la fiabilité de l'oxyde sont des obstacles majeurs à la fabrication de dispositifs MOSFET avancés en SiC. Des solutions alternatives ont été développées pour surmonter ces problèmes. Toutefois, les MOSFETs en SiC ont seulement été récemment commercialisés, principalement en raison des problèmes de fiabilité. Le procédé de fabrication de MOSFETs adapté à la production de masse est encore un défi.Les principaux efforts réalisés dans le cadre de cette thèse concernent le développement des MOSFETs en SiC par l'amélioration du procédé d'oxydation pour la fabrication de l'oxyde de grille. Un nouveau procédé basé sur l'oxydation par Rapid Thermal Processing (RTP) est démontré. De plus, les mécanismes physiques associés à la formation de l'oxyde et des propriétés de l'interface SiO2/SiC sont proposés. Ce procédé d'oxydation a été testé sur le SiC hexagonal (4H-SiC) et le SiC cubique (3C-SiC). En outre, la technologie d'oxydation étudiée a été intégrée dans la fabrication de MOSFETs en 4H-SiC. La fiabilité des composants a été aussi évaluée pour des stress en tension jusqu'à des températures de fonctionnement de 300C.Power electronic devices are mainly based on the mature and very well established silicon technology. However, silicon exhibits some important limitations regarding power losses, operation temperature and speed of switching. Furthermore, unfortunately the successful silicon technology has almost reached its physical limits. Hence, a new generation of power devices based on new materials must be developed to face the future global energetic challenges. Nowadays, the most promising semiconductor material is silicon carbide (SiC). SiC is increasingly considered as the best candidate to overcome the intrinsic limitations of silicon in developing high-power and high-temperature electronic devices. It shows the best trade-off between theoretical characteristics and real commercial availability of the starting material and maturity of its technological processes.This thesis is focused on SiC-based power devices, particularly, on one of the major issues in SiC technology: the gate oxidation process. Indeed, SiC can be easily oxidized to form a thin silicon dioxide (SiO2) layer. This provides a unique opportunity to develop power Metal Oxide Semiconductor (MOS) devices, as in the Si-based technology. SiC-based power MOSFETs are expected to have great potential for high-speed and low-loss switching devices. Unfortunately, the oxide/SiC interface quality and oxide reliability are major barriers to the fabrication of advanced SiC power MOSFET devices. Alternative solutions have been developed to overcome these problems. However, SiC MOSFETs have only been recently commercially available, mainly due to reliability concerns. The MOSFET process suitable for mass production is still a challenge. The main efforts carried out in the framework of this thesis are addressed towards the development of SiC MOSFETs by improving the current gate oxide process state-of-the-art. A newly gate oxidation process based on rapid thermal processing is demonstrated, and the physical mechanisms associated with oxide formation and the SiO2/SiC interface properties are proposed. This oxidation process has been tested on hexagonal SiC (4H-SiC) and cubic SiC (3C-SiC). Furthermore, the investigated oxidation processing technology is integrated into the fabrication of reliable 4H-SiC MOSFETs, and the bias-stress instability has been evaluated up to operating temperatures of 300 C.MONTPELLIER-BU Sciences (341722106) / SudocSudocFranceF