Backward and Forward Compatibility

In response to the European Union (EU) Restriction of Hazardous Substances (RoHS) and other countries’ impending lead-free directives, the electronics industry is moving toward lead-free soldering. Total lead-free soldering requires not only lead-free solder paste but also lead-free printed circuit board (PCB) finish and lead-free component/packages. Transitioning tin-lead (SnPb) soldering to totally lead-free soldering is a complex issue and involves movement of the whole electronics industry supply chain. In reality, there is a transition period

Mitigating tin whisker risks: theory and practice

Discusses the growth mechanisms of tin whiskers and the effective mitigation strategies necessary to reduce whisker growth risks. This book covers key tin whisker topics, ranging from fundamental science to practical mitigation strategies. The text begins with a review of the characteristic properties of local microstructures around whisker and hillock grains to identify why these particular grains and locations become predisposed to forming whiskers and hillocks. The book discusses the basic properties of tin-based alloy finishes and the effects of various alloying elements on whisker formation, with a focus on potential mechanisms for whisker suppression or enhancement for each element. Tin whisker risk mitigation strategies for each tier of the supply chain for high reliability electronic systems are also described

Effects of Reflow Profile and Thermal Conditioning on Intermetallic Compound Thickness for SnAgCu Soldered Joints

Purpose – The purpose of this paper is to investigate the effects of reflow time, reflow peak temperature, thermal shock and thermal aging on the intermetallic compound (IMC) thickness for Sn3.0Ag0.5Cu (SAC305) soldered joints. Design/methodology/approach – A four-factor factorial design with three replications is selected in the experiment. The input variables are the peak temperature, the duration of time above solder liquidus temperature (TAL), solder alloy and thermal shock. The peak temperature has three levels, 12, 22 and 32°C above solder liquidus temperatures (or 230, 240 and 250°C for SAC305 and 195, 205, and 215°C for SnPb). The TAL has two levels, 30 and 90 s. The thermally shocked test vehicles are subjected to air-to-air thermal shock conditioning from -40 to 125°C with 30 min dwell times (or 1 h/cycle) for 500 cycles. Samples both from the initial time zero and after thermal shock are cross-sectioned. The IMC thickness is measured using scanning electron microscopy. Statistical analyses are conducted to compare the difference in IMC thickness growth between SAC305 solder joints and SnPb solder joints, and the difference in IMC thickness growth between after thermal shock and after thermal aging. Findings – The IMC thickness increases with higher reflow peak temperature and longer time above liquidus. The IMC layer of SAC305 soldered joints is statistically significantly thicker than that of SnPb soldered joints when reflowed at comparable peak temperatures above liquidus and the same time above liquidus. Thermal conditioning leads to a smoother and thicker IMC layer. Thermal shock contributes to IMC growth merely through high-temperature conditioning. The IMC thickness increases in SAC305 soldered joints after thermal shock or thermal aging are generally in agreement with prediction models such as that proposed by Hwang. Research limitations/implications – It is still unknown which thickness of IMC layer could result in damage to the solder. Practical implications – The IMC thickness of all samples is below 3 µm for both SnPb and SAC305 solder joints reflowed at the peak temperature ranging from 12 to 32°C above liquidus temperature and at times above liquidus ranging from 30 to 90 s. The IMC thickness is below 4 µm after subjecting to air-to-air thermal shock from -40 to 125°C with 30 min dwell time for 500 cycles or thermal aging at 125°C for 250 h. Originality/value – The paper reports experimental results of IMC thickness at different thermal conditions. The application is useful for understanding the thickness growth of the IMC layer at various thermal conditions

Drop Test Reliability of Lead-free Chip Scale Packages

This paper presents the drop test reliability of 0.5 mm pitch lead-free chip scale packages (CSPs). Fifteen 0.5 mm pitch CSPs were assembled on a standard JEDEC drop reliability test board with Sn3.0Ag0.5Cu lead-free solder. Eight boards were edge-bonded with a UV-cured acrylic; eight boards were edge- bonded with a thermal-cured epoxy; and twelve boards were assembled without edge bonding. Half of the edge-bonded test boards were subjected to drop tests at a peak acceleration of 1500 G with a pulse duration of 0.5 ms, and the other half subjected to drop tests at a peak acceleration of 2900 G with a pulse duration of 0.3 ms. Half of the test boards without edge bonding were subjected to drop tests at a peak acceleration of 900 G with a pulse duration of 0.7 ms, and the other half subjected to drop tests at a peak acceleration of 1500 G with a pulse duration of 0.5 ms. Two drop test failure detection systems were used in this study to monitor the failure of solder joints: a high-speed resistance measurement system and a post-drop static resistance measurement system. The high-speed resistance measurement system, which has a scan frequency of 50 KHz and a 16-bit signal width, is able to detect intermittent failures during the short drop impact duration. Statistics of the number of drops to failure for the 15 component locations on each test board are reported. The effect of component position on drop test reliability is discussed. The test results show that the drop test performance of edge-bonded CSPs is five to eight times better than the CSPs without edge bonding. However, the drop test reliability of edge-bonded CSPs with the thermal-cured epoxy is different from that with edge-bonded CSPs with the UV-cured acrylic. The solder crack location and crack area are characterized with the dye penetrant method. The fracture surfaces are studied using scanning electron microscopy (SEM)

Pb-Free Assembly, Rework, and Reliability Analysis of

Abstract A team of NEMI companies collaborated for three years to develop Pb-free assembly and rework processes for doublesided, 14-layer, printed circuit boards (PCB) in two thicknesses (0.093" and 0.135") with electrolytic NiAu and Immersion Ag surface finishes. This work followed the initial SMT manufacturing feasibility effort carried out by the first NEMI Pb-free development team (1999)(2000)(2001)(2002). All SMT assembly, PTH wave assembly and component rework processes were carried out on production equipment. Various test vehicles including the reliability test board were used in a multiphase development project to develop Pb-free assembly and rework parameters and temperature profiles prior to a 100-board process technology verification build. Following the double-sided SMT and wave assembly build, half of the printed circuits assemblies were passed through a series of representative component rework protocols. Each build group was then subjected to a series of mechanical and thermal reliability stress tests, including 5700 cycles of 0 to 100°C, followed by failure analysis. A special test board was designed utilizing a high temperature laminate designed for Pb-free soldering. Approximately 30% of the assemblies were SnPb control samples. This paper will present the Pbfree SMT assembly and rework development process using the NEMI Sn3.9Ag0.6Cu solder, and results of the reliability stress tests. The rework of large, thick PCB's with Pb-free solder poses a significant challenge to the industry. The lesson's learned and recommendations for future work will be discussed. Introduction The 2002 NEMI Roadmap acknowledged that the first NEMI Pb-free project had laid the foundations for Pb-free manufacturing processes, including the selection and recommendation of the Sn3.9Ag0.6Cu solder alloy. However, it was recognized that more development work was needed for rework and wave soldering and to extend manufacturing process development to larger higher thermal mass printed circuit assemblies. To accomplish this, a new project was initiated that included manufacturing-level studies on the assembly and rework of large, complex, high thermal mass component board assemblies, representing IPC Class 2

Drop Impact Reliability of Edge-Bonded Lead-Free Chip Scale Packages

This paper presents the drop test reliability results for edge-bonded 0.5 mm pitch lead-free chip scale packages (CSPs) on a standard JEDEC drop reliability test board. The test boards were subjected to drop tests at several impact pulses, including a peak acceleration of 900 Gs with a pulse duration of 0.7 ms, a peak acceleration of 1500 Gs with a pulse duration of 0.5 ms, and a peak acceleration of 2900 Gs with a pulse duration of 0.3 ms. A high-speed dynamic resistance measurement system was used to monitor the failure of the solder joints. Two edge-bond materials used in this study were a UV-cured acrylic and a thermal-cured epoxy material. Tests were conducted on CSPs with edge-bond materials and CSPs without edge bonding. Statistics of the number of drops-to-failure for the 15 component locations on each test board are reported. The test results show that the drop test performance of edge-bonded CSPs is five to eight times better than the CSPs without edge bonding. Failure analysis was performed using dye-penetrant and scanning electron microscopy (SEM) methods. The most common failure mode observed is pad lift causing trace breakage. Solder crack and pad lift failure locations are characterized with the dye-penetrant method and optical microscopy