23 research outputs found
Prototype ATLAS IBL Modules using the FE-I4A Front-End Readout Chip
The ATLAS Collaboration will upgrade its semiconductor pixel tracking
detector with a new Insertable B-layer (IBL) between the existing pixel
detector and the vacuum pipe of the Large Hadron Collider. The extreme
operating conditions at this location have necessitated the development of new
radiation hard pixel sensor technologies and a new front-end readout chip,
called the FE-I4. Planar pixel sensors and 3D pixel sensors have been
investigated to equip this new pixel layer, and prototype modules using the
FE-I4A have been fabricated and characterized using 120 GeV pions at the CERN
SPS and 4 GeV positrons at DESY, before and after module irradiation. Beam test
results are presented, including charge collection efficiency, tracking
efficiency and charge sharing.Comment: 45 pages, 30 figures, submitted to JINS
Design of analog front-ends for the RD53 demonstrator chip
The RD53 collaboration is developing a large scale pixel front-end chip, which will be a tool to evaluate the performance of 65 nm CMOS technology in view of its application to the readout of the innermost detector layers of ATLAS and CMS at the HL-LHC. Experimental results of the characterization of small prototypes will be discussed in the frame of the design work that is currently leading to the development of the large scale demonstrator chip RD53A to be submitted in early 2017. The paper is focused on the analog processors developed in the framework of the RD53 collaboration, including three time over threshold front-ends, designed by INFN Torino and Pavia, University of Bergamo and LBNL and a zero dead time front-end based on flash ADC designed by a joint collaboration between the Fermilab and INFN. The paper will also discuss the radiation tolerance features of the front-end channels, which were exposed to up to 800 Mrad of total ionizing dose to reproduce the system operation in the actual experiment
Planar pixel sensors for the ATLAS upgrade: beam tests results
Results of beam tests with planar silicon pixel sensors aimed towards the ATLAS Insertable B-Layer and High Luminosity LHC (HL-LHC) upgrades are presented. Measurements include spatial resolution, charge collection performance and charge sharing between neighbouring cells as a function of track incidence angle for different bulk materials. Measurements of n-in-n pixel sensors are presented as a function of fluence for different irradiations. Furthermore p-type silicon sensors from several vendors with slightly differing layouts were tested. All tested sensors were connected by bump-bonding to the ATLAS Pixel read-out chip. We show that both n-type and p-type tested planar sensors are able to collect significant charge even after integrated fluences expected at HL-LHC
Planar pixel sensors for the ATLAS upgrade: beam tests results
Results of beam tests with planar silicon pixel sensors aimed towards the
ATLAS Insertable B-Layer and High Luminosity LHC (HL-LHC) upgrades are
presented. Measurements include spatial resolution, charge collection
performance and charge sharing between neighbouring cells as a function of
track incidence angle for different bulk materials. Measurements of n-in-n
pixel sensors are presented as a function of fluence for different
irradiations. Furthermore p-type silicon sensors from several vendors with
slightly differing layouts were tested. All tested sensors were connected by
bump-bonding to the ATLAS Pixel read-out chip. We show that both n-type and
p-type tested planar sensors are able to collect significant charge even after
integrated fluences expected at HL-LHC.Comment: 28 pages, 27 figures, published on Journal of Instrumentation (JINST
Planar pixel sensors for the ATLAS upgrade: beam tests results
Results of beam tests with planar silicon pixel sensors aimed towards the
ATLAS Insertable B-Layer and High Luminosity LHC (HL-LHC) upgrades are
presented. Measurements include spatial resolution, charge collection
performance and charge sharing between neighbouring cells as a function of
track incidence angle for different bulk materials. Measurements of n-in-n
pixel sensors are presented as a function of fluence for different
irradiations. Furthermore p-type silicon sensors from several vendors with
slightly differing layouts were tested. All tested sensors were connected by
bump-bonding to the ATLAS Pixel read-out chip. We show that both n-type and
p-type tested planar sensors are able to collect significant charge even after
integrated fluences expected at HL-LHC.Comment: 28 pages, 27 figures, published on Journal of Instrumentation (JINST
Planar pixel sensors for the ATLAS upgrade: beam tests results
Results of beam tests with planar silicon pixel sensors aimed towards the
ATLAS Insertable B-Layer and High Luminosity LHC (HL-LHC) upgrades are
presented. Measurements include spatial resolution, charge collection
performance and charge sharing between neighbouring cells as a function of
track incidence angle for different bulk materials. Measurements of n-in-n
pixel sensors are presented as a function of fluence for different
irradiations. Furthermore p-type silicon sensors from several vendors with
slightly differing layouts were tested. All tested sensors were connected by
bump-bonding to the ATLAS Pixel read-out chip. We show that both n-type and
p-type tested planar sensors are able to collect significant charge even after
integrated fluences expected at HL-LHC.Comment: 28 pages, 27 figures, published on Journal of Instrumentation (JINST
Test results and prospects for RD53A, a large scale 65 nm CMOS chip for pixel readout at the HL-LHC
The CERN RD53 collaboration was founded to tackle the extraordinary challenges associated with the design of pixel readout chips for the innermost layers of particle trackers at future high energy physics experiments. Around 20 institutions are involved in the collaboration, which has the support of both ATLAS and CMS experiments. The goals of the collaboration include the comprehensive understanding of radiation effects in the 65 nm technology, the development of tools and methodology to efficiently design large complex mixed signal chips and, ultimately, the development of a full size readout chip featuring a 400 Ă— 400 pixel array with 50ÎĽm pitch. In August 2017, the collaboration submitted the large scale chip RD53A, integrating a matrix of 400 Ă— 192 pixels and embodying three different analog front-end designs. This work discusses the characteristic of the RD53A chip, with some emphasis on the analog processors, and presents the first test results on the pixel array