35 research outputs found

    Describing the syntax and semantics of UML statecharts in a heterogeneous modelling environment

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    In this paper UML statechart diagrams are used as an example of a generic approach to integrating a visual language in a heterogeneous modelling and simulation environment.Asystem represented in a visual language is syntactically defined as an attributed graph, with well-formedness rules specified by a set of firstorder predicates over the abstract syntax of the graph. The language semantics are specified by an Abstract State Machine (ASM) parameterized with syntacticallycorrect attributed graphs. In this paper the key issues in the definition of UML statechart semantics are highlighted.Yan Jin, Robert Esser and Jörn W. Jannec

    Trace-based manycore partitioning of stream-processing applications

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    Application performance on these processor array platforms is highly sensitive to how functionality is physically placed on the device, as this choice crucially determines communication latencies and congestion patterns of the on-chip inter-core communication. The problem of identifying the best, or just a good enough, partitioning and placement does not, in general, admit to an analytic solution, and its combinatorial nature makes solving it by pure experimentation impractical. This paper presents an approach that maps stream programs onto processor arrays using trace analysis as a technique for evaluating candidate solutions and for suggesting alternatives

    Partitioning And Optimization Of High Level Stream Applications For Multi Clock Domain Architectures

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    In this paper we propose a design methodology to partition dataflow applications on a multi clock domain architecture. This work shows how starting from a high level dataflow representation of a dynamic program it is possible to reduce the overall power consumption without impacting the performances. Two different approaches are illustrated, both based on the post-processing and analysis of the causation trace of a dataflow program. Methodology and experimental results are demonstrated in an at-size scenario using an MPEG-4 Simple Profile decoder

    Multi-clock domain optimization for reconfigurable architectures in high-level dataflow applications

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    This paper proposes a new design methodology to partition streaming applications onto a multi clock domain architecture. The objective is to save power by running different parts of the application at the lowest possible clock frequency that will not violate the throughput requirements. The solution involves partitioning the application into an appropriate number of clock domains, and then assigning each of those domains a clock frequency. Two different approaches are illustrated, both based on the post-processing and analysis of the causation trace of a dataflow program. Methodology and initial experimental results are demonstrated in an at-size scenario using an MPEG-4 Simple Profile decoder implemented in a FPGA platform
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