Standard Ternary Inverter Based on Junction Leakage-Enhanced Nanoscale Planar CMOS and Its Variation Immunity

We propose a novel standard ternary inverter (STI) based on nanoscale planar CMOS technology for a compact design of multi-valued logic (MVL). By enhancing junction band-to-band tunneling (BTBT) leakage with high channel doping for STI operation, the 'third' intermediate state (VINT) can be successfully obtained at VDD/2 in the conventional binary CMOS inverter. It is demonstrated that the variability of the intermediate level (??VINT<80mV) can be allowable into the worst noise margin (>0.1V)

Demonstration of standrad ternary inverter based on CMOS technology

We demonstrate a standard ternary inverter (STI) by using gate-last CMOS process with novel I-V characteristics based on off-state mechanism. Though the controllable ????? and ????? with respective design parameters, STI operation at VDD= 1 V have been investigated with static noise margin (SNM) of 210 mV

Ultra-Low Standby Power and Static Noise-Immune Standard Ternary Inverter Based on Nanoscale Ternary CMOS Technology

We demonstrate ternary CMOS (T-CMOS)-based standard ternary inverter (STI) for compact and powerscalable multi-valued logic (MVL) circuits. The distinguished mechanism of VG-independent junction band-to-band tunneling (BTBT) for ternary logic has been successfully obtained by CMOS process with a few pA/m level which enables STI operation with ultra-low static power consumption of 7.7 pW/m. Through the STI performance investigation with various T-CMOS structures by using TCAD simulation, advanced nanoscale bulk tri-gate (TG) ternary FinFET (TFinFET) shows highly noise-immune STI operation with a larger static noise margin (SNM) of 94% to the ideal SNM (230mV) than 86% of bulk planar T-CMOS and 75% of SOI TCMOS technology

CMOS-Compatible Ternary Device Platform for Physical Synthesis of Multi-valued Logic Circuits

We propose the feasible and scalable ternary CMOS (T-CMOS) device platform for a fully CMOS-compatible physical synthesis of multi-valued logic (MVL) circuits. By developing the compact model of T-CMOS and verifying the physical model parameters with experimental data, the T-CMOS design framework based on standard ternary inverter (STI) is presented for static noise margin (SNM) enhancement and performance analysis of ternary logic gates

Gate induced drain leakage reduction with analysis of gate fringing field effect on high-kappa/metal gate CMOS technology

We suggest the optimum permittivity for a high-kappa/metal gate (HKMG) CMOS structure based on the trade-off characteristics between the fringing field induced barrier lowering (FIBL) and gate induced drain leakage (GIDL). By adopting the high-kappa gate dielectric, the GIDL from the band-to-band tunneling at the interface of gate and lightly doped drain (LDD) is suppressed with wide tunneling width owing to the enhanced fringing field, while the FIBL effects is degenerated as the previous reports. These two effects from the gate fringing field are studied extensively to manage the leakage current of HKMG for low power applications. (C) 2015 The Japan Society of Applied Physicclose0

Low Leakage III-V/Ge CMOS FinFET Design for High-Performance Logic Applications with High-kappa Spacer Technology

We propose a novel optimized design strategy by considering the correlated effects of high-kappa gate oxide and spacer dielectric on GIDL and DIBL for high performance nanoscale CMOS with III-V/Ge channel tri-gate FinFET structure. By investigating the transition of GIDL mechanism from vertical to lateral direction in 14-nm InAs n-FinFET and Ge p-FinFET with abrupt and high drain doping, the lateral GIDL is suppressed as 1/100 by high-kappa spacer with high drive current of 1 mA/um and lower leakage current than 100 nA/um which works on lower operation voltage (V-DD = 0.63 V). in addition, DIBL is also suppressed below 100 mV/V by taking relatively lower-K gate oxide than the high-kappa spacer

Multi-Valued Logic Based on CMOS technology

We propose a novel standard ternary inverter (STI) based on nanoscale planar CMOS technology for a compact design of multi-valued logic (MVL). By enhancing junction band-to-band tunneling (BTBT) leakage with high channel doping for STI operation, the ???third??? intermediate state (VINT) can be successfully obtained at VDD/2 in the conventional binary CMOS inverter. The junction BTBT off-leakage variation effects are investigated by considering doping fluctuation in the mixed-mode device simulation. It is demonstrated that the variability of the intermediate level (DVINT< 80 mV) can be allowable into the worst noise margin (> 0.1 V) of STI operation