Design of analog mixer for RF front-end

This paper presents design of analog mixer using modified Gilbert cell topology for use in RF front. The proposed circuit gives improvement in its performance. The input RF and LO frequency is set to 2500MHz and 2250MHz respectively, resulting in an output IF frequency of 250MHz.The simulation results show that the conversion gain is 9.605dB, single-sideband noise figure is 9.448dB and output IM3 intercept point is 15.764dBm with power consumption of 24.732mW. It uses supply voltage of 1.8V and the circuit layout has been obtained using CMOS 0.18μm technology fabrication

Analysis of transmit-receive diversity in Rayleigh fading

We analyze the error performance of a wireless communication system employing transmit-receive diversity in Rayleigh fading. By focusing on the complex Gaussian statistics of the independent and identically distributed entries of the channel matrix, we derive a formula for the characteristic function (c.f.) of the maximum output signal-to-noise ratio. We use this c.f. to obtain a closed-form expression of the symbol error probability (SEP) for coherent binary keying. The method is easily extended to obtain the SEP for the coherent reception of M-ary modulation schemes

Design of a 1.8V on-chip voltage generator for applications in low voltage transceiver

This paper presents a design of on-chip voltage generator for applications in battery-less low voltage transceiver. The supply voltage for this on-chip voltage generator is obtained from mutual inductive coupling through radio frequency (RF) electromagnetic field which is able to generate 150mV peak voltage. This on-chip voltage generator is used to generate a supply voltage for a low voltage low power transceiver. Simulation results showed that it is able to give a constant voltage of 1.8V with 30μA of current from an input of 150mV peak voltage. This chip is realized using a CMOS 0.18μm process

An improved power consumption circuit of a 5.7 GHz variable-gain low noise amplifier (VGLNA) for RF applications

A low voltage topology that uses a capacitively coupled resonating element has been introduced using 0.18 mum CMOS technology. The topology utilizes the decoupling scheme to dc isolate circuit elements that are connected in series and share a common dc current. A 5.7 GHz variable-gain low noise amplifier (VGLNA) is presented with simulation results exhibiting a noise figure of 1.02 dB, power gain of 19.41 dB with gain tuning range of 6 dB and IIP3 of -1.11 dBm. The power consumption reported is 12.88 mW at supply of Vdd = 0.7 V for power optimization circuit. Simulation results show that the proposed VGLNA has better noise performance and improved power consumption compared to the conventional cascode VGLNA

A low power 2.4 GHz variable-gain low noise amplifier for wireless applications

A 2.4 GHz variable-gain low noise amplifier (VGLNA) intended for use in a Wide-band Code Division Multiple Access receiver was designed in 0.18 um CMOS process for low voltage and low power applications. Rivaling classical designs using voltage mode approach, this design used the current mode approach, utilizing the current mirror principle to obtain a controllable gain range from 8.26 dB to 16.95 dB with good input and output return losses. By varying the current through the widths of transistors and a bias resistor, the VGLNA was capable of exhibiting 8 dB gain tuning range without degrading the noise figure. Therefore, higher gain was possible at lower current and thus at lower power consumption. Total power consumption simulated was 4.63 mW from a 1 V supply and this gave a gain/power quotient of 3.66 dB/mW. Comparing this with available published data, it was observed that this work demonstrated a good gain tuning range and the lowest noise figure with such power consumption

A full rate concatenated space-frequency and space-time OFDM over Naftali fading channels

In this paper we investigate 2 transmit and 1 receive (2Tx:1Rx) space-frequency orthogonal frequency division multiplexing (SF-OFDM) and space-time OFDM (ST-OFDM) concatenated with convolutional channel coding as a redundancy method to combat channel impairments. We built our SF and ST-OFDM on top of our coded OFDM (COFDM) with coding rate of 1/4 and constraint length of 10. We simulate our concatenated SF-OFDM and ST-OFDM over a multipath fading channel using Naftali 802.11 channel model under different delay spreads in relation to outdoor environment. Concatenated SF- OFDM performs slightly better than ST-OFDM at delay spread of 2.0 microseconds, but both are almost comparable at all other delay spreads. These two schemes outperforms other schemes such as single antenna coded OFDM and Alamouti's Space-Time Block Code (STBC) under these conditions by as much as 10 dB at BER of 104

A simplified sphere decoding algorithm for MIMO transmission system

In sphere decoding the choice of sphere radius is crucial to excellent performance. In Chan-Lee sphere decoding -based algorithm, the problem of choosing initial radius has been solved by making the radius sufficiently large, thus increasing the size of the search region. In this paper we present maximum likelihood decoding using simplified sphere decoder as apposed to the original sphere decoder for the detection of cubic structure quadrature amplitude modulation symbols. This simple algorithm based on Chan-Lee sphere decoder allows the search for closest lattice point in a reduced complexity manner compared to original sphere decoder for multiple input multiple output system with perfect channel state information at the receiver. Results show symbol error rate has stabilized even at very low initial value of the square radius

Design of front end of a RF receiver

Radio frequency (RF) circuit is having a rapid growth in wireless telecommunication. The increasing demand for higher quality and popularity of wireless services have urged the development of low cost multi-functional and reconfigurable RF front end modules fabricated from advanced device technologies. The RF front end is generally defined as everything between antenna and the intermediate frequency (IF) stage. For a receiver, this "between" area in eludes filter, low noise amplifier, mixer and local oscillator. The circuit was designed based on CMOS 0.18 um technology to input a 2. 5 GHz RF signal and local oscillation of 2.25 GHz. This results in an output IF frequency of 250 MHz. The RF front end circuit had been simulated using Advanced Design System to obtain the proper output frequency and determining the system performance

Floating-gate MOS structures and applications

Floating-gate MOS transistor (FGMOS) has proved to be suitable for low-voltage analog applications, owing to its threshold voltage programmability. This tutorial paper presents FGMOS based circuit structures and their applications in analog signal processing. The FGMOS based current mirror and its application as voltage controlled current source has been presented. The performance of these structures has been verified using PSpice simulations for 0.5 im CMOS technology at 0.75 V

A novel ternary CDMA code for TPSK modulation scheme

In code division multiple access (CDMA), two or more chips are grouped together to form symbols and each symbol is transmitted during the symbol period. The phase shift keying (PSK) modulation techniques map the digital baseband data into two or more possible signals by varying the phase of a radio frequency (RF) carrier. The recently proposed PSK scheme called ternary PSK (TPSK) scheme can convey three possible symbols. In this paper, a novel ternary based CDMA sequence so-called large area synchronous even ternary (LAS-ET) sequence is introduced to increase spectrum efficiency in TPSK scheme. Its sequence duty ratio and cross-correlation are analyzed. The performance analysis of this sequence is compared with the large area synchronous (LAS) sequence in term of symbol error rate and chip error rate (CER) over various channel models. It is shown that TPSK scheme in LAS-ET sequence outperforms LAS sequence in terms of CER evaluation. At the same time, the spectrum efficiency is doubled when a pair of chips in LAS-ET sequence is mapped into one symbol