Using System-on-a-Programmable-Chip Technology to Design Embedded Systems

This paper describes the tools, techniques, and devices used to design embedded products with system–on-a-chip (SoC) type solutions using a large Field Programmable Gate Array (FPGA) with an internal processor core. This new FPGA-based approach is called system-on-a-programmable-chip (SoPC ). The performance tradeoffs present in SoPC systems is compared to more traditional design approaches. Commercial devices, processor cores, and CAD tool flows are described. The issues in SoPC hardware/software design tradeoffs are examined and three example SoPC designs are presented as case studies

Using Rapid Prototyping in Computer Architecture Design Laboratories

This paper describes the undergraduate computer architecture courses and laboratories introduced at Georgia Tech during the past two years. A core sequence of six required courses for computer engineering students has been developed. In this paper, emphasis is placed upon the new core laboratories which utilize commercial CAD tools, FPGAs, hardware emulators, and a VHDL based rapid prototyping approach to simulate, synthesize, and implement prototype computer hardware

An introductory digital design course using a low–cost autonomous robot

This paper describes a new digital design laboratory developed for undergraduate students in this electrical and computer engineering curriculum. A top-down rapid prototyping approach with commercial computer-aided design tools and field-programmable logic devices (FPLDs) is used for laboratory projects. Students begin with traditional transistor–transistor logic-based projects containing a few gates and progress to designing a simple 16-bit computer, using very high-speed integrated circuits hardware description language (VHDL) synthesis tools and an FPLD. To help motivate students, the simple computer design is programmed to control a small autonomous robot with two servo drive motors and several sensors. The laboratory concludes with a team-based design project using the robot

Participant and spectator scaling of spectator fragments in Au + Au and Cu + Cu collisions at √sNN = 19.6 and 22.4 GeV

Spectator fragments resulting from relativistic heavy ion collisions, consisting of single protons and neutrons along with groups of stable nuclear fragments up to nitrogen (Z=7), are measured in PHOBOS. These fragments are observed in Au+Au (√sNN =19.6GeV) and Cu+Cu (22.4 GeV) collisions at high pseudorapidity (η). The dominant multiply-charged fragment is the tightly bound helium (α), with lithium, beryllium, and boron all clearly seen as a function of collision centrality and pseudorapidity. We observe that in Cu+Cu collisions, it becomes much more favorable for the α fragments to be released than lithium. The yields of fragments approximately scale with the number of spectator nucleons, independent of the colliding ion. The shapes of the pseudorapidity distributions of fragments indicate that the average deflection of the fragments away from the beam direction increases for more central collisions. A detailed comparison of the shapes for α and lithium fragments indicates that the centrality dependence of the deflections favors a scaling with the number of participants in the collision.United States. Department of Energy (Grant DE-AC02-98CH10886)United States. Department of Energy (Grant DE-FG02-93ER40802)United States. Department of Energy (Grant DE-FG02-94ER40818)United States. Department of Energy (Grant DE-FG02-94ER40865)United States. Department of Energy (Grant DE-FG02- 99ER41099)United States. Department of Energy (Grant DE-AC02-06CH11357)National Science Foundation (U.S.) (Grant 9603486)National Science Foundation (U.S.) (Grant 0072204)National Science Foundation (U.S.) (Grant 0245011

The design and performance of a parallel computer architecture for simulation

Ph.D.Glenn Batema

System-on-a-Programmable-Chip Development Platforms in the Classroom

Abstract—This paper describes the authors ’ experiences using a system-on-a-programmable-chip (SOPC) approach to support the development of design projects for upper-level undergraduate students in their electrical and computer engineering curriculum. Commercial field-programmable gate-array (FPGA)-based SOPC development boards with reduced instruction set computer (RISC) processor cores are used to support a wide variety of student design projects. A top-down rapid prototyping approach with commercial FPGA computer-aided design tools, a C compiler targeted for the RISC soft-processor core, and a large FPGA with memory is used and reused to support a wide variety of student projects. Index Terms—Altera, field-programmable gate array (FPGA), microblaze, Nios, processor core, system on a chip (SOC), system on a programmable chip (SOPC), Xilinx. I

Multiple Objective Evolutionary Algorithms for Independent, Computationally Expensive Objective Evaluations Approved by:

This thesis is dedicated to my wife and eight children. Without their support this would not have been possible. iii ACKNOWLEDGEMENTS I would like to acknowledge the following who have made this thesis possible: 1. Dr. Darrell Lamm, my mentor and friend for the past 15 years, spent countless hours over these years listening and directing my research efforts. 2. Dr. Mark Clements, my thesis advisor, had the patience to take on a part-time student for this long road. 3. Georgia Tech Research Institute, my employer, provided funding for the qualifying exam, Ph.D research, development of the PRESTO software, and tuition. Without their support I would have never begun this research. 4. Charles Carstensen, of GTRI, saw the potential of Genetic Algorithm application to flare pattern design against infra-red surface to are missiles. Fortunately, he saw the potential before the shooting started