Boride-enhanced diffusion in silicon:bulk and surface layers

\u3cp\u3eEpitaxial silicon bonde layers, located at the surface or within the bulk of single-crystal silicon, give rise to enhanced diffusion of B during annealing. A submonolayer buried boride layer releases ≈0.4 interstitials per B atom in the layer, generating a transient diffusion enhancement in the range of 10-100 for several minutes at 900 °C. The resulting profile broadening is comparable to that caused by ion implantation damage. At the same temperature, surface boride layers generate a diffusion enhancement of ∼6, part of which arises from the B diffusion flux and part from the chemical influence of the boride layer.\u3c/p\u3

Low-energy implantations of decaborane (B10H14) ion clusters in silicon wafers

\u3cp\u3eLow-energy implantation with decaborane (B\u3csub\u3e10\u3c/sub\u3eH\u3csub\u3e14\u3c/sub\u3e) ion clusters is suitable for ultra-shallow junction formation. Using a high-voltage research implanter with a microwave ion source, decaborane implantation has been performed at energies in the range 2.8 to 440 keV, with doses up to 10\u3csup\u3e14\u3c/sup\u3e decaborane/cm\u3csup\u3e2\u3c/sup\u3e(10\u3csup\u3e15\u3c/sup\u3e B atoms/cm\u3csup\u3e2\u3c/sup\u3e). A study of the implantation damage shows that the number of displaced Si lattice atoms in the near-surface region is considerably larger for the decaborane implants than for the corresponding B\u3csup\u3e+\u3c/sup\u3e implants. Ultra-shallow dopant profiles have been achieved by 2.8 keV B\u3csub\u3e10\u3c/sub\u3eH\u3csub\u3e14\u3c/sub\u3e \u3csup\u3e+\u3c/sup\u3e implantation, equivalent to an energy of 255 eV per incoming B atom. In such a case the B peak concentration is located only a few atomic layers below the Si surface, and implantation damage is virtually absent. Transient enhanced diffusion effects during rapid thermal annealing were negligible, apart from the slight movement associated with migration of interstitial B atoms onto substitutional sites.\u3c/p\u3

The effect of thin oxide layers on shallow junction formation

\u3cp\u3eThis paper studies the influence of thin oxide screening, layers on the, formation of shallow junctions by low-energy B. implantation and rapid thermal annealing. F011 screening oxides, in the range ftom 0 to 10 nm, it is f found! that the trade-off between junction depth and\ shet resistance ps is not affected! as long, as the implanted dose is adjusted. to compensate. for B trapping in the. oxide. F011 a fixed: implant: dose and enengy, however, minute variations in the oxide, thickness have, a. large influence on pI'ho which limits the reproducibility of. the junctionformation process.\u3c/p\u3

Physical and chemical degradation behavior of sputtered aluminum doped zinc oxide layers for Cu(In,Ga)Se\u3csub\u3e2\u3c/sub\u3e solar cells

\u3cp\u3eSputtered aluminum doped zinc oxide (ZnO:Al) layers on borosilicate glass were exposed to damp heat (85 C/85% relative humidity) for 2876 h to accelerate the physical and chemical degradation behavior. The ZnO:Al samples were characterized by electrical, compositional and optical measurements before and after degradation. Hall measurements show that the carrier concentration stayed constant, while the Hall mobility decreased and the overall resistivity thus increased. This can be explained by the increase of potential barriers at the grain boundaries due to the occurrence of space charge regions caused by additional electron trapping sites. X-Ray Diffraction and optical measurements show that the crystal structure and transmission in the range 300-1100 nm do no change, hereby confirming that the bulk structure stays constant. Furthermore, on the surface, white spots appeared, containing elements that migrated from the glass, like silicon and calcium, which reacted with elements from the environment, including oxygen, carbon and chlorine. Depth profiling showed that the increase of the potential barrier is caused by the diffusion of H \u3csub\u3e2\u3c/sub\u3eO/OH\u3csup\u3e-\u3c/sup\u3e through the grain boundaries leading to the formation of Zn(OH)\u3csub\u3e2\u3c/sub\u3e or similar species or adsorption of species. They also indicate the presence of chloride and sulfide in the top layer and the possible presence of Zn\u3csub\u3e5\u3c/sub\u3e(OH)\u3csub\u3e8\u3c/sub\u3eCl\u3csub\u3e2\u3c/sub\u3e·H \u3csub\u3e2\u3c/sub\u3eO and Zn\u3csub\u3e4\u3c/sub\u3eSO\u3csub\u3e4\u3c/sub\u3e(OH)\u3csub\u3e6\u3c/sub\u3e·nH \u3csub\u3e2\u3c/sub\u3eO\u3c/p\u3

Work function stability of thermal ALD Ta(Si)N gate electrodes on HfO \u3csub\u3e2\u3c/sub\u3e

\u3cp\u3eTa(Si)N films deposited by thermal atomic layer deposition (ALD) have been investigated as potential gate electrode materials in advanced CMOS devices. The work function (Φ \u3csub\u3em\u3c/sub\u3e) of these films was determined by high-frequency capacitance-voltage measurements (HF-CV) on a thickness series of ALD HfO \u3csub\u3e2\u3c/sub\u3e. Depositing films at 400 and 500°C with an optimized pulse sequence, two films with Si content of 3 and 8 at%, respectively, were studied. Both Ta(Si)N films gave Φ \u3csub\u3em\u3c/sub\u3e of 4.7 ± 0.1 eV, also after high-temperature thermal treatments, with the 400°C deposition giving more reliable electrical performance.\u3c/p\u3

Laminated CeO\u3csub\u3e2\u3c/sub\u3e/HfO\u3csub\u3e2\u3c/sub\u3e high-k gate dielectrics grown by pulsed laser deposition in reducing ambient

\u3cp\u3eCeO\u3csub\u3e2\u3c/sub\u3e and HfO\u3csub\u3e2\u3c/sub\u3e dielectric layers were deposited in an Ar+(5%)H\u3csub\u3e2\u3c/sub\u3e gas mixture by Pulsed Laser Deposition (PLD) on Si (100). A CeO\u3csub\u3e2\u3c/sub\u3e-Ce\u3csub\u3e2\u3c/sub\u3eO\u3csub\u3e3\u3c/sub\u3e transformation is achieved by deposition in a reducing ambient. It is also shown that in-situ post deposition anneal efficiently oxidizes Ce\u3csub\u3e2\u3c/sub\u3eO\u3csub\u3e3\u3c/sub\u3e layers to CeO \u3csub\u3e2\u3c/sub\u3e. The properties of CeO\u3csub\u3e2\u3c/sub\u3e/HfO\u3csub\u3e2\u3c/sub\u3e laminated structures deposited in reducing ambient and compared with binary oxide layers of CeO\u3csub\u3e2\u3c/sub\u3e and HfO\u3csub\u3e2\u3c/sub\u3e. The effect of the layer sequence, individual layer thickness and deposition temperature on the structural and electrical properties of the laminates were investigated. It is found that the layer sequence of the laminates affects the crystallinity of the layers and changes the electrical properties. The amorphous laminate with a CeO\u3csub\u3e2\u3c/sub\u3e starting layer with 4 nm physical thickness and an EOT of 2 nm, has the lowest J@V\u3csub\u3efb\u3c/sub\u3e-1 V=1.88 × 10\u3csup\u3e-7\u3c/sup\u3e A/cm\u3csup\u3e2\u3c/sup\u3e. The best EOT-J\u3csub\u3eg\u3c/sub\u3e trade off is achieved by the laminated layers with a CeO \u3csub\u3e2\u3c/sub\u3e starting layer deposited at 520°C. copyright The Electrochemical Society.\u3c/p\u3