Flexible Spare Core Placement in Torus Topology based NoCs and its validation on an FPGA

In the nano-scale era, Network-on-Chip (NoC) interconnection paradigm has gained importance to abide by the communication challenges in Chip Multi-Processors (CMPs). With increased integration density on CMPs, NoC components namely cores, routers, and links are susceptible to failures. Therefore, to improve system reliability, there is a need for efficient fault-tolerant techniques that mitigate permanent faults in NoC based CMPs. There exists several fault-tolerant techniques that address the permanent faults in application cores while placing the spare cores onto NoC topologies. However, these techniques are limited to Mesh topology based NoCs. There are few approaches that have realized the fault-tolerant solutions on an FPGA, but the study on architectural aspects of NoC is limited. This paper presents the flexible placement of spare core onto Torus topology-based NoC design by considering core faults and validating it on an FPGA. In the first phase, a mathematical formulation based on Integer Linear Programming (ILP) and meta-heuristic based Particle Swarm Optimization (PSO) have been proposed for the placement of spare core. In the second phase, we have implemented NoC router addressing scheme, routing algorithm, run-time fault injection model, and fault-tolerant placement of spare core onto Torus topology using an FPGA. Experiments have been done by taking different multimedia and synthetic application benchmarks. This has been done in both static and dynamic simulation environments followed by hardware implementation. In the static simulation environment, the experimentations are carried out by scaling the network size and router faults in the network. The results obtained from our approach outperform the methods such as Fault-tolerant Spare Core Mapping (FSCM), Simulated Annealing (SA), and Genetic Algorithm (GA) proposed in the literature. For the experiments carried out by scaling the network size, our proposed methodology shows an average improvement of 18.83%, 4.55%, 12.12% in communication cost over the approaches FSCM, SA, and GA, respectively. For the experiments carried out by scaling the router faults in the network, our approach shows an improvement of 34.27%, 26.26%, and 30.41% over the approaches FSCM, SA, and GA, respectively. For the dynamic simulations, our approach shows an average improvement of 5.67%, 0.44%, and 3.69%, over the approaches FSCM, SA, and GA, respectively. In the hardware implementation, our approach shows an average improvement of 5.38%, 7.45%, 27.10% in terms of application runtime over the approaches SA, GA, and FSCM, respectively. This shows the superiority of the proposed approach over the approaches presented in the literature.publishedVersio

Flexible Spare Core Placement in Torus Topology based NoCs and its validation on an FPGA

In the nano-scale era, Network-on-Chip (NoC) interconnection paradigm has gained importance to abide by the communication challenges in Chip Multi-Processors (CMPs). With increased integration density on CMPs, NoC components namely cores, routers, and links are susceptible to failures. Therefore, to improve system reliability, there is a need for efficient fault-tolerant techniques that mitigate permanent faults in NoC based CMPs. There exists several fault-tolerant techniques that address the permanent faults in application cores while placing the spare cores onto NoC topologies. However, these techniques are limited to Mesh topology based NoCs. There are few approaches that have realized the fault-tolerant solutions on an FPGA, but the study on architectural aspects of NoC is limited. This paper presents the flexible placement of spare core onto Torus topology-based NoC design by considering core faults and validating it on an FPGA. In the first phase, a mathematical formulation based on Integer Linear Programming (ILP) and meta-heuristic based Particle Swarm Optimization (PSO) have been proposed for the placement of spare core. In the second phase, we have implemented NoC router addressing scheme, routing algorithm, run-time fault injection model, and fault-tolerant placement of spare core onto Torus topology using an FPGA. Experiments have been done by taking different multimedia and synthetic application benchmarks. This has been done in both static and dynamic simulation environments followed by hardware implementation. In the static simulation environment, the experimentations are carried out by scaling the network size and router faults in the network. The results obtained from our approach outperform the methods such as Fault-tolerant Spare Core Mapping (FSCM), Simulated Annealing (SA), and Genetic Algorithm (GA) proposed in the literature. For the experiments carried out by scaling the network size, our proposed methodology shows an average improvement of 18.83%, 4.55%, 12.12% in communication cost over the approaches FSCM, SA, and GA, respectively. For the experiments carried out by scaling the router faults in the network, our approach shows an improvement of 34.27%, 26.26%, and 30.41% over the approaches FSCM, SA, and GA, respectively. For the dynamic simulations, our approach shows an average improvement of 5.67%, 0.44%, and 3.69%, over the approaches FSCM, SA, and GA, respectively. In the hardware implementation, our approach shows an average improvement of 5.38%, 7.45%, 27.10% in terms of application runtime over the approaches SA, GA, and FSCM, respectively. This shows the superiority of the proposed approach over the approaches presented in the literature

ALDH1A inhibition sensitizes colon cancer cells to chemotherapy

Abstract Background Recent evidence in cancer research, developed the notion that malignant tumors consist of different subpopulations of cells, one of them, known as cancer stem cells, being attributed many important properties such as enhanced tumorigenicity, proliferation potential and profound multidrug resistance to chemotherapy. Several key stem cells markers were identified in colon cancer. In our study we focused on the aldehyde dehydrogenase type 1 (ALDH1) expression in colon cancer-derived cell lines HT-29/eGFP, HCT-116/eGFP and LS-180/eGFP, and its role in the chemoresistance and tumorigenic potential. Methods The effect of pharmacological inhibition of ALDH activity by diethylaminobenzaldehyde (DEAB) and also effect of molecular inhibition by specific siRNA was evaluated in vitro in cultures of human colorectal cell lines. The expression level of different isoenzymes of aldehyde dehydrogenase was determined using qPCR. Changes in cell biology were evaluated by expression analysis, western blot and apoptosis assay. The efficiency of cytotoxic treatment in the presence of different chemotherapeutic drugs was analyzed by fluorimetric assay. Tumorigenicity of cells with specific ALDH1A1 siRNA was tested in xenograft model in vivo. Results Treatment by DEAB partially sensitized the tested cell lines to chemotherapeutics. Subsequently the molecular inhibition of specific isoforms of ALDH by ALDH1A1 or ALDH1A3 siRNA led to sensitizing of cell lines HT-29/eGFP, HCT-116/eGFP to capecitabine and 5-FU. On the model of athymic mice we observed the effect of molecular inhibition of ALDH1A1 in HT-29/eGFP cells by siRNA. We observed inhibition of proliferation of subcutaneous xenografts in comparison to control cells. Conclusion This research, verifies the significance of the ALDH1A isoforms in multidrug resistance of human colorectal cancer cells and its potential as a cancer stem cell marker. This provides the basis for the development of new approaches regarding the treatment of patients with colorectal adenocarcinoma and potentially the treatment of other tumor malignancies