Course development in IC manufacturing

A traditional curriculum in electrical engineering separates semiconductor processing courses from courses in circuit design. As a result, manufacturing topics involving yield management and the study of random process variations impacting circuit behaviour are usually vaguely treated. The subject matter of this paper is to report a course developed at Texas A&M University, USA, to compensate for the aforementioned shortcoming. This course attempts to link technological process and circuit design domains by emphasizing aspects such as process disturbance modeling, yield modeling, and defect-induced fault modeling. In a rapidly changing environment where high-end technologies are evolving towards submicron features and towards high transistor integration, these aspects are key factors to design for manufacturability. The paper presents the course's syllabus, a description of its main topics, and results on selected project assignments carried out during a normal academic semeste

Laser : a layout sensitivity explorer : report and user's manual

As the IC pattern resolutions tend 10 become smaller the layout geometry plays a more important role in IC yield. The probability that a chip will fail is directly related to the way that the IC artwork is laid out. By examining the possible places where catastrophic defects may occur one can prevent potential faults, and thus estimate the reliability of the design. Rrealistic yield simulation tools must consider the specific layout. It is, therefore, ideal a CAE tool that automatically explores and predicts the layout reliability for real environmentai conditions prevailing in the manufacturing line. We present a system capable of interactively finding the critical areas for shorts and breaks, the sensitivity, and the yield of the IC artwork,for any range of defect sizes. The implementation is based on a simple scanline algorithm and performs only one layout extraction for any span of defect size

In place detection of internal and external corrosion for underground steel casing pipes

Corrosion monitoring and early detection of pits and wall thinning is important to the gas and petroleum industry. A new noncontact AC electromagnetic induction system has been developed for monitoring and detecting corrosion in multistring casing configuration. The system includes a sonde which has a transmitter coil and three receiver coils, with the transmitter circuit generating three low different frequencies at the same time. The multifrequency AC current through the transmitter coil induces in the pipe wall a longitudinal alternating magnetic field which is sensed by three receiver coils located at different distances. The multiple transmitter frequencies and the multiple transmitter-receiver spacings can provide the maximum flexibility and the most extensive information in quantitatively determining the total wall thickness in single, dual, and three-string casing configuration. The transmitter circuits are designed to work at up to 175°C without having a second breakdown. Since the dynamic range of received signal is very broad and the "road note" is severe, the high-stable high-accurate band pass filter and hard limiters are adopted in the receiver circuit and phase detect circuit. In order to discriminate internal and external corrosion of casing pipes, an "electronic caliper" is incorporated in the system to detect the average circumferential diameter of casing pipes. Therefore, the complete logging of the casing pipes can be accomplished with a single sca

1-D discrete time CNN with multiplexed template hardware

While VLSI of CNNs has seen significant progress in two-dimensional signal processing little has been done for one-dimensional applications such as audio signal processing and 1-D filtering. The paper presents a discrete-time programmable cellular neural network suitable for these kind of applications. The proposed VLSI implementation is based on the well-known S2I technique that among other properties minimizes clock feedthrough effects. This feature renders an accurate signal processing unit. The system's main building blocks are an analog shift register and a switched current multiplier. Yet, the system architecture is novel by itself. Namely, the number of multipliers has been minimized by sharing the multipliers between the A*y and B*u products during the various phases of the controlling clock. The paper presents detailed simulation results of the system architectur

The analysis of spot defect induced faults in MOS circuits

A strategy for modeling spot defect induced faults by their corresponding Boolean functions is developed. The presented strategy is based on the principle of local conduction path analysis. This way of modeling is much more general in the sense that all kinds of faults are unified by one concept, the Boolean function. In this way testing related applications can be done efficiently and can maintain a high qualit

An adaptive digital caliration of multi-step A/D converters.

A novel digital technique for efficient calibration of static errors in high-speed, high-resolution, multi-step ADCs is proposed. The parameter update within the calibration method is extended to include and correct effects of temperature and process variations. Additionally, to guide the verification process with the information obtained through monitoring process variations, expectation-maximization method is employed. The algorithm is evaluated on a prototype multi-step ADC converter with embedded dedicated sensors fabricated in standard single poly, six metal 0.09-樨 CMOS

DNA computing based on chaos

In this paper a new approach for the realization of the DNA computing paradigm is presented. It exploits the natural richness of chaotic dynamics to efficiently generate and process coded binary sequences following the DNA computing framework introduced by Adleman (1994). The new method is discussed and some simulation results regarding the Directed Hamiltonian Path problem are presente

One-dimensional discrete-time CNN with multiplexed template-hardware

This paper presents a novel discrete-time and fully programmable cellular neural network (CNN) suitable for processing one-dimensional (1-D) signals. As 1-D signals are typically very long sequences, the system consists of a linear analog shift register for data I/O coupled to a 1×n CNN array. In addition to the 1-D CNN architecture, a unique feature of our implementation is that the number of multipliers needed to implement both CNN templates has been minimized. This is conceivable because the multipliers are multiplexed between the A*y and B*u products during alternating phases of the controlling clock. The CNN system has been implemented in current mode based on the S2I technique using MOSIS Orbit 2 µm CMOS technology. The paper presents a thorough behavioral analysis of the new architecture, circuit-level implementations, and corresponding measured experimental result

On the design and implementation of a wafer yield editor

An interactive environment is presented for the analysis of yield information required on modern integrated circuit manufacturing lines. The system estimates wafer yields and wafer-yield variations, quantifies regional yield variations within wafers, identifies clusters in wafers and/or in lots, and is able to predict wafer yields via simple simulation tools. An analysis approach based on site yields makes the system independent of the product and of the technology. The analysis technique makes it possible to investigate the effects of both correlated and uncorrelated sources of yield loss. The statistical information obtained can be used to study changes in the technological process. Graphical displays in the form of wafer maps are used to represent the spatial distribution of dice in the wafer. Capabilities for such as radial and angular distribution analyses, among others, are provided to examine data, and hypothetical wafer maps are created to visualize and predict simulated wafer yield

Calibration and Debugging of Multi-step Analog to Digital Converters

This paper reports a new approach for debugging of the analog to digital converters based on process monitoring and extended design-for-test implementation. The circuit is re-configured in such a way that all sub-blocks are analysed and tested for their full input range allowing full observability and controllability of the analog to digital converter. To set initial data, estimate the parameter update and to guide the test, dedicated monitors have been designed. Additionally, the second presented algorithm allow circuit calibration without explicit need for any dedicated test signal nor requires a part of the conversion time. It works continuously and with every signal applied to the ADC