30 research outputs found

    Prevalence of major depression in preschool children

    Full text link
    The prevalence of preschool major depressive disorder (MDD) was studied in the community. The whole population of children between 3 and 6 years attending preschool nurseries in three areas (one urban, one rural and one suburban) in Spain (n = 1,427) were contacted. Selection was by a two-stage procedure. At stage I, the ESDM 3-6, a screening measure for preschool depression, was used to identify a sample for more intensive interviewing. Sensitivity and specificity of the cut-off point of the ESDM 3–6 had been previously tested in a pilot study (n = 229). During the first stage, 222 preschool children (15.6%) were found to be probable depressives, because they scored 27 or more, the cut-off used. At stage II, the children were interviewed and diagnosed by the consensus of two clinicians, blind to the ESDM 3-6 results. DSM-IV diagnostic criteria were used to define caseness. A total of 16 children (1.12%) met the MDD criteria. The prevalence by areas was urban 0.87%, rural 0.88%, suburban 1.43%. Sex distribution prevalence was 1:1. This study is a contribution to the scarce epidemiology of preschool depression in the community

    TERRESTRIAL LASER SCANNER AND FAST CHARACTERIZATION OF SUPERFICIAL LESIONS IN ARCHITECTURAL DIAGNOSIS

    Get PDF
    The development of massive data captures techniques (MDC) in recent years, such as the Terrestrial Laser Scanner (TLS), raises the possibility of developing new assessment procedures for architectural heritage. The 3D models that it is able to obtain is a great potential tool, both for conservation purposes and for historical and architectural studies. The paper proposes a simple, non-invasive methodology for the assessment of masonry vaults from point clouds which makes it possible to obtain relevant data about the formal anomalies. The methodology is tested in Tortosa’s Gothic Cathedral’s vaults, where the geometrical differences between vaults, a priori equal, are identified and related with the partially known construction phases. The procedure can be easily used on any other vaulted construction of any kind, but is especially useful to deal with the complex geometry of Gothic masonry vaults

    High prevalence of strongyloidiasis in spain : A hospital-based study

    Get PDF
    Strongyloidiasis is a prevailing helminth infection ubiquitous in tropical and subtropical areas, however, seroprevalence data are scarce in migrant populations, particularly for those coming for Asia. This study aims at evaluating the prevalence of S. stercoralis at the hospital level in migrant populations or long term travellers being attended in out-patient and in-patient units as part of a systematic screening implemented in six Spanish hospitals. A cross-sectional study was conducted and systematic screening for S. stercoralis infection using serological tests was offered to all eligible participants. The overall seroprevalence of S. stercoralis was 9.04% (95%CI 7.76-10.31). The seroprevalence of people with a risk of infection acquired in Africa and Latin America was 9.35% (95%CI 7.01-11.69), 9.22% (7.5-10.93), respectively. The number of individuals coming from Asian countries was significantly smaller and the overall prevalence in these countries was 2.9% (95%CI −0.3-6.2). The seroprevalence in units attending potentially immunosuppressed patients was significantly lower (5.64%) compared with other units of the hospital (10.20%) or Tropical diseases units (13.33%) (p < 0.001). We report a hospital-based strongyloidiasis seroprevalence of almost 10% in a mobile population coming from endemic areas suggesting the need of implementing strongyloidiasis screening in hospitalized patients coming from endemic areas, particularly if they are at risk of immunosuppression

    Out-of-Order Access to Parallel Memories in order to Reduce Conflicts in Vector Processors

    No full text
    The performance of a vector processor accessing vectors is strongly dependent on the conflicts produced in the memory subsystem. These conflicts create holes in the data flow between processor and memory, delaying the task of the functional units. This paper proposes an out-oforder access to vectors in order to reduce the average memory access time in vector processors. Previous investigations into out-of-order access to vectors have attempted to increment the conflict-free access families of strides. The goal of this work is to reduce the conflicts when multiple vectors are concurrently accessed in memory. Keywords: Conflict-free access, out-of-order, concurrent vector access, parallel memory system, vector processor. 1. Introduction The performance of a vector processor is strongly related to the bandwidth of a memory subsystem (number of accesses per cycle). Due to the fact that the processor speed is greater than the memory speed, it is necessary to develop architecture features t..

    Evaluation of A+B=K conditions without carry propagation

    No full text

    Increasing the Effective Memory Bandwidth in Multivector Processors

    No full text
    In the memory system of multivector processors, the interferences between concurrent vector streams cause the loss of cycles that makes the effective throughput be lower than the required throughput. Then, the work of the functional units is delayed. Using the classical order to access the vector stream elements, the vector stream references the memory modules using a temporal distribution that depends on the element specification pattern; in general, different specification patterns determine different temporal distributions of memory modules. Concurrent vector streams using different temporal distributions to access the memory modules could imply the presence of memory module conflicts even if the request rate of all the concurrent streams to every memory module is less than or equal to it service rate. This paper proposes an access order to reference the vector stream elements. This new order is imposed by a temporal distribution of memory modules that reduces the average memory acc..

    Hardware Support to Reduce Conflicts between Vector Streams

    No full text
    The performance of a vector processor accessing vectors is strongly dependent on the conflicts produced in the memory subsystem. These conflicts delay the task of the functional units. This paper proposes a hardware support to access vectors in order to reduce the average memory access time in vector processors. 1. Introduction The performance of a vector processor is strongly related to the bandwidth of a memory subsystem (number of accesses per cycle). Due to the fact that the processor speed is greater than the memory speed, it is necessary to develop architecture features to support parallelism in the memory subsystem. The most used technique is multiple memory modules that are accessed independently. A conflict appears when two or more references are concurrently issued to the same memory module. This situation causes the performance of the memory subsystem to be lower than the highest reachable. Conflicts are an important factor in the performance degradation of vector processor..

    Reducing Inter-Vector-Conflicts in Complex Memory Systems

    No full text
    In vector processors, the concurrent memory access of several vector streams causes interconflicts between the references. In a complex memory system where several memory modules are mapped in every bus the number of conflicts increases because the bus must be shared by the vector streams. In addition to the memory module access conflicts, bus access conflicts could appear, and also couplings of both conflicts. This paper proposes an access order to the vector stream elements and a mapping model of memory modules in buses that reduce the interconflicts in the steady-state. Keywords: Complex Memory System, Vector Stream, Inter-conflicts, Inter-Complex Conflicts, Stride. 1. Introduction The most common data structures in vector processors are vectors stored in consecutive positions in memory. The access patterns are regular and, sometimes, consecutive positions are accessed. The memory module reservation time is, in general, much longer than the processor cycle time. Therefore, the perf..
    corecore