A new BIST scheme for low-power and high-resolution DAC testing

A BIST scheme for testing on chip DAC is presented in this paper. We discuss the generation of on chip testing stimuli and the measurement of digital signals with a narrow-band digital filter. We validate the scheme with software simulation and point out the possibility of ADC BIST with verified DACicus-journals

SSE Projekt HDL-VMS - HDL's, Verhaltensmodellierung, Mixed-Signal-Modellierung und -Simulation, Spezifikationserfassung Schlussbericht

SIGLEAvailable from TIB Hannover: DtF QN1(93,53) / FIZ - Fachinformationszzentrum Karlsruhe / TIB - Technische InformationsbibliothekBundesministerium fuer Bildung, Wissenschaft, Forschung und Technologie, Bonn (Germany)DEGerman