An analysis of pattern usage in CS1 courses

When designing and planning the implementation of software, expert programmers rarely think at the syntactic level. Instead, they think at higher levels of abstraction, mentally "chunking" groups of lines of code into a single abstraction. These chunks have been referred to as patterns in CS1 literature and pattern-oriented instruction has been proposed. This thesis builds on the existing literature by analyzing instructor solutions to the assessments of a diverse collection of seven CS1 courses to identify the patterns that students are expected to learn. In particular, I make two contributions. First, I provide a catalog of the patterns that I identified. Second, I present analysis based on detailed records of which patterns occurred in which assessments. Results include the relative frequency of each pattern in all the assessments and the order in which patterns appeared in each course. I hope that this analysis enables instructors to be more conscientious and explicit in how these patterns are introduced to their students

Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration

DNN accelerators are often developed and evaluated in isolation without considering the cross-stack, system-level effects in real-world environments. This makes it difficult to appreciate the impact of System-on-Chip (SoC) resource contention, OS overheads, and programming-stack inefficiencies on overall performance/energy-efficiency. To address this challenge, we present Gemmini, an open-source*, full-stack DNN accelerator generator. Gemmini generates a wide design-space of efficient ASIC accelerators from a flexible architectural template, together with flexible programming stacks and full SoCs with shared resources that capture system-level effects. Gemmini-generated accelerators have also been fabricated, delivering up to three orders-of-magnitude speedups over high-performance CPUs on various DNN benchmarks. * https://github.com/ucb-bar/gemminiComment: To appear at the 58th IEEE/ACM Design Automation Conference (DAC), December 2021, San Francisco, CA, US