Expanded delta networks for very large parallel computers

In this paper we analyze a generalization of the traditional delta network, introduced by Patel [21], and dubbed Expanded Delta Network (EDN). These networks provide in general multiple paths that can be exploited to reduce contention in the network resulting in increased performance. The crossbar and traditional delta networks are limiting cases of this class of networks. However, the delta network does not provide the multiple paths that the more general expanded delta networks provide, and crossbars are to costly to use for large networks. The EDNs are analyzed with respect to their routing capabilities in the MIMD and SIMD models of computation.The concepts of capacity and clustering are also addressed. In massively parallel SIMD computers, it is the trend to put a larger number processors on a chip, but due to I/O constraints only a subset of the total number of processors may have access to the network. This is introduced as a Restricted Access Expanded Delta Network of which the MasPar MP-1 router network is an example

Self-routing lowest common ancestor networks

Multistage interconnection networks (MIN's) allow communication between terminals on opposing sides of a network. Lowest Common Ancestor Networks (LCAN's) [1] have switches capable of connecting bi-directional links in a permutation pattern that additionally permits communication between terminals on the same side. Self-routing LCAN's have interesting permutation routing capabilities and are highly partionable. This paper characterizes self-routing LCAN's and analyzes their permutation routing capabilities. It is shown that the routing network of the CM-5 is a particular instance of an LCAN

Lowest common ancestor interconnection networks

Lowest Common Ancestor (LCA) networks are built using switches capable of connecting u + d inputs/outputs in a permutation pattern. For n source nodes and I stages of switches, n/d switches are used in stage l - n/d - u/d in stage l - 2, and in general , n-u^l-i-l/d^l-i switches in stage i. The resulting hierarchical structure possesses interesting connectivity and permutational properties. A full characterization of LCA networks is presented together with a permutation routing algorithm for a family of LCA networks. The algorithm uses the network itself to collect and disseminate information about the permutation. A schedule of O(dp log_d/u n) passes is obtained with a switch set-up cost factor of O(log_d/u n) (p is the minimum number of passes that an algorithm with global knowledge schedules)

Matrix elements and duality for type 2 unitary representations of the Lie superalgebra gl(m|n)

The characteristic identity formalism discussed in our recent articles is further utilized to derive matrix elements of type 2 unitary irreducible $gl(m|n)$ modules. In particular, we give matrix element formulae for all gl(m|n) generators, including the non-elementary generators, together with their phases on finite dimensional type 2 unitary irreducible representations. Remarkably, we find that the type 2 unitary matrix element equations coincide with the type 1 unitary matrix element equations for non-vanishing matrix elements up to a phase.Comment: 24 pages. arXiv admin note: text overlap with arXiv:1311.424

The effect of FPU architecture on a dynamic precision algorithm for the solution of differential equations

Solution of lnitial Value Problems (IVPs) is an important application in scientific computing. Methods for solving these problems use techniques for reducing the error and increasing the speed of the computation. This paper introduces a class of algorithms which dynamically reconfigure their operating parameters to reduce the computation time. By dynamically varying the precision of the arithmetic being performed, it is possible to obtain dramatic speedups on certain architectures when solving IVPs. This paper illustrates how various architectures impact on a dynamic precision version of the Runge-Kutta-Fehlberg algorithm. It is shown that a speedup of over 30 percent is possible for both massively parallel processors and vector supercomputers

Cavity sideband cooling of a single trapped ion

We report a demonstration and quantitative characterization of one-dimensional cavity cooling of a single trapped 88Sr+ ion in the resolved sideband regime. We measure the spectrum of cavity transitions, the rates of cavity heating and cooling, and the steady-state cooling limit. The cavity cooling dynamics and cooling limit of 22.5(3) motional quanta, limited by the moderate coupling between the ion and the cavity, are consistent with a simple model [Phys. Rev. A 64, 033405] without any free parameters, validating the rate equation model for cavity cooling.Comment: 5 pages, 4 figure

Shortest paths in orthogonal graphs

Orthogonal graphs were introduced as a simple but powerful tool for the description and analysis of a class of interconnection networks. Routing, and hence finding shortest paths between any two nodes of an orthogonal graph, becomes an important problem. It is shown in this paper that routing in this class of graphs reduces to a node covering problem in the bipartite coverage graph of the orthogonal graph. A minimum cover clearly leads to a shortest path. In general, the problem of finding the mínimum node cover in a bipartite graph is NP-complete. However, the bipartite coverage graphs corresponding to orthogonal graphs have a regular pattern of edges. This allows the development of a routing algorithm which results in a minimum cover. The procedure executes in polynomial time in the number of bit-nodes of the bipartite graph. It therefore results in a shortest path algorithm whose time complexity is quadratic in the logarithm of the number of nodes in the original orthogonal graph