Schedule-Aware Performance Estimation of Communication Architecture for Efficient Design Space Exploration

In this paper,we are concerned about performance estimation of bus-based communication architectures assuming that task partitioning and scheduling on processing elements are already determined. Since communication overhead is dynamic and unpredictable due to bus contention, a simulation-based approach seems inevitable for accurate performance estimation. However, it is too time-consuming to be used for exploring the wide design space of bus architectures. We propose a static performance-estimation technique based on a queueing analysis assuming that the memory traces and the task schedule information are given. We use this static estimation technique as the first step in our design space exploration framework to prune the design space drastically before applying a simulation-based approach to the reduced design space. Experimental results show that the proposed technique is several orders of magnitude faster than a trace-driven simulation while keeping the estimation error within 10% consistently in various communication architecture configurations.This work was supported by the National Research Laboratory under Program M1-0104-00-0015, Brain Korea 21 Project, and the IT-SoC project. ICT at Seoul National University provided research facilities for this study

Energy Optimization for Latency- and Qaulity-Constrained Video Applications

This paper proposes an energy optimization technique for latency and quality constrained video applications. It consists of two key techniques: frame-skipping technique and buffering technique. While buffering increases the slack time utilization at the OS level, frame skipping increases the slack time itself at the application level, and both enhance the effectiveness of the DVS technique. We use an H.263 encoder application as a test vehicle to which the proposed technique is applied. Experiments demonstrate that the proposed technique achieves noticeable energy reduction satisfying the given latency and video quality constraints.National Research Laboratory Program No. M1- 0104-00-0015 and the Brain Korea 21 Project supported this work. The Institute of Computer Technology at Seoul National University provided research facilities

Dynamic Voltage Scheduling with Buffers in Low-Power Multimedia Applications

Power-efficient design of multimedia applications becomes more important as they are used increasingly in many embedded systems. We propose a simple dynamic voltage scheduling technique which suits multimedia applications well and, in case of soft real-time applications, allows all idle intervals of the processor to be fully exploited by using buffers. Our main theme is to determine the minimum buffer size to maximize energy saving in three cases: (i) single-task, (ii) multiple-subtask and (iii) multi-task. We also present a technique of adjusting task deadlines for further reducing energy consumption in the multiple-subtask and multi-task cases. Unlike other DVS techniques using buffers, we guarantee to meet the real-time latency constraint. Experimental results show that the proposed technique does indeed achieve significant power reduction in real-world multimedia applications.This work was supported by National Research Laboratory Program (No. M1-0104-00-0015) and the Brain Korea 21 Project. The ICT at Seoul National University provided research facilities for this study

Efficient exploration of on-chip bus architectures and memory allocation

Separation between computation and communication in system design allows the system designer to explore the communication architecture independently of component selection and mapping. In this paper we present an iterative two-step exploration methodology for bus-based on-chip communication architecture and memory allocation, assuming that memory traces from the processing elements are given from the mapping stage. The proposed method uses a static performance estimation technique to reduce the large design space drastically and quickly, and applies a trace-driven simulation technique to the reduced set of design candidates for accurate performance estimation. Since local memory traffic as well as shared memory traffic are involved in bus contention, memory allocation is considered as an important axis of the design space in our technique. The viability and efficiency of the proposed methodology are validated by two reallife examples, 4-channel digital video recorder (DVR) and an equalizer for OFDM DVB-T receiver

Dynamic Voltage Scheduling Technique for Low-Power Multimedia Applications Using Buffers

As multimedia applications are used increasingly in many embedded systems, power efficient design for the applications becomes more important than ever. This paper proposes a simple dynamic voltage scheduling technique, which suits the multimedia applications well. The proposed technique fully utilizes the idle intervals with buffers in a variable speed processor. The main theme of this paper is to determine the minimum buffer size to achieve the maximum energy saving in three cases: single-task, multiple subtasks, and multi-task. Experimental results show that the proposed technique is expected to obtain significant power reduction for several real-world multimedia applications

Schedule-Aware performance estimation of communication architecture for efficient design space exploration

Abstract—In this paper, we are concerned about performance estimation of bus-based communication architectures assuming that task partitioning and scheduling on processing elements are already determined. Since communication overhead is dynamic and unpredictable due to bus contention, a simulation-based approach seems inevitable for accurate performance estimation. However, it is too time-consuming to be used for exploring the wide design space of bus architectures. We propose a static performance-estimation technique based on a queueing analysis assuming that the memory traces and the task schedule information are given. We use this static estimation technique as the first step in our design space exploration framework to prune the design space drastically before applying a simulation-based approach to the reduced design space. Experimental results show that the proposed technique is several orders of magnitude faster than a trace-driven simulation while keeping the estimation error within 10 % consistently in various communication architecture configurations. Index Terms—Communication architecture, design space exploration, performance estimation, queueing theory. I

Dynamic Voltage Scheduling with Buffers in Low-Power Multimedia Applications

this paper is an on-line inter-task DVS technique that can exploit the VST fully using buffers. We target multimedia applications where a buffering delay is tolerable within a latency constraint. The proposed technique is better than the previous inter-task DVS techniques because it fully utilizes both WST and VST. And it is better than the intra-task DVS techniques because it uses much fewer voltage changes at run-time. We aim to minimize the voltage fluctuation because a constant voltage level gives the ideal performanc

Dynamic Voltage Scaling for Real-Time Multi-task Scheduling Using Buffers

This paper proposes energy efficient real-time multi-task scheduling (EDF and RM) algorithms by using buffers. The buffering technique overcomes a drawback of previous approaches by utilizing the slack time of a system fully. It increases the CPU utilization and averages the workload of a system, so it enhances the effectiveness of the DVS technique. We target multimedia applications where a slight buffering delay is tolerable within a latency constraint. We modify the state transition and queue handling mechanism of multi-task scheduling in the kernel. In experiments, our algorithms achieve up to 44% of energy consumption saving for EDF scheduling and 49% for RM scheduling with realistic task set configurations and reasonable machine specifications