Riflessioni sulle rime irraggiate nei ferimenti cranici d\u2019arma da fuoco. Parte prima.

none4noneIesurum A.; Vercelli A.; Invernizzi E.; Montanari E.Iesurum A.; Vercelli A.; Invernizzi E.; Montanari E

Forensic Pathology by Scanning Electron Microscopy

An atlas of scanning electronic microscopy (SEM) may turn out to be useful for studying the many issues that are submitted to the coroner\u2019s attention. It may also offer interesting ideas to experts of biomedical subjects who are still interested in pushing back the frontiers of scientific explanation. Many of these are at the limits of disciplines that today are contiguous, and had, until a short time ago, been separated by distances that were more apparent than substantial, in the tumultuous implementation of the models designed to explain the technologies

Considerazioni in tema di patologia forense riguardo una raccolta di preparati istologici del primo'900

esame di un araccolta di preparati istologici del primo '900 da un punto di vista tecnico (leggibilit\ue0 a fini diagnostici) e riflessione sulle patologie emergenti a seconda delle epoche e periodi

A 68.6fs_rms-Total-integrated-Jitter and 1.5us-Locking-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching

To pursue the ever-growing trend in mobile data-rates, modern transceivers exploit carrier aggregation and high-order modulations, at the price of calling for ultra-low jitter (below 100fs) and frequency-agile local oscillators. Although the bang-bang digital-PLL (BBPLL) architecture can meet the stringent 5G jitter requirements at low power consumption and silicon area [1], its inability to quickly recover from a frequency jump, caused by the narrow linear range of a bang-bang phase detector (BBPD), has so far prevented its application when frequency agility is an important requirement. A high-resolution and wide-range time-to-digital converter (TDC), rather than a BBPD, would solve this issue at the price of larger power and area. As a matter of fact, fast-hopping ADPLLs using multibit TDCs have been demonstrated in applications with relaxed jitter specifications [2], [3]. To break the trade-off between frequency agility and jitter-power product, auxiliary frequency-acquisition loops have been recently adopted in BBPLL architectures [1], [4], [5]. Those auxiliary loops, based on extra BBPDs, control the digitally-controlled-oscillator (DCO) frequency with a gain larger than that of the main loop, thus decreasing the settling time. Unfortunately, above a certain control-gain value, the system nonlinearity introduces an unwanted dependence between the main and auxiliary loops, limiting locking time to several thousands of reference cycles