77 research outputs found

    Fabrication of submicron planar Gunn diode

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    We present, for the first time, the fabrication process for a submicron planar Gunn diode in In<sub>0.53</sub>Ga<sub>0.47</sub>As on an InP substrate operating at 265 GHz. A novel two stage lift off method has been developed to achieve a submicron gaps between contacts down to 135 nm with widths up to 120 μm

    180nm metal gate, high-k dielectric, implant-free III--V MOSFETs with transconductance of over 425 μS/μm

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    Abstract: Data is reported from 180 nm gate length GaAs n-MOSFETs with drive current (Ids,sat) of 386 μA/μm (Vg=Vd =1.5 V), extrinsic transconductance (gm) of 426 μS/μm, gate leakage ( jg,limit) of 44 nA/cm2, and on resistance (Ron) of 1640 Ω μm. The gm and Ron metrics are the best values reported to date for III-V MOSFETs, and indicate their potential for scaling to deca-nanometre dimensions

    SiGe p-channel MOSFETs with tungsten gate

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    A self-aligned SiGe p-channel MOSFET tungsten gate process with 0.1 μm resolution is demonstrated. Interface charge densities of MOS capacitors realised with the low pressure sputtered tungsten process are comparable with thermally evaporated aluminium gate technologies (5×1010cm-2 and 2×1011 cm -2 for W and Al, respectively). Initial results from 1 μm gate length SiGe p-channel MOSFETs using the tungsten-based process show devices with a transconductance of 33 mS/mm and effective channel mobility of 190 cm

    Square Root Singularity in Boundary Reflection Matrix

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    Two-particle scattering amplitudes for integrable relativistic quantum field theory in 1+1 dimensions can normally have at most singularities of poles and zeros along the imaginary axis in the complex rapidity plane. It has been supposed that single particle amplitudes of the exact boundary reflection matrix exhibit the same structure. In this paper, single particle amplitudes of the exact boundary reflection matrix corresponding to the Neumann boundary condition for affine Toda field theory associated with twisted affine algebras a2n(2)a_{2n}^{(2)} are conjectured, based on one-loop result, as having a new kind of square root singularity.Comment: 10 pages, latex fil

    1 &#956;m gate length, In<sub>0.75</sub>Ga<sub>0.25</sub>As channel, thin body n-MOSFET on InP substrate with transconductance of 737&#956;S/&#956;m

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    The first demonstration of implant-free, flatband-mode In&lt;sub&gt;0.75&lt;/sub&gt;Ga&lt;sub&gt;0.25&lt;/sub&gt;As channel n-MOSFETs is reported. These 1 &#956;m gate length MOSFETs, fabricated on a structure with average mobility of 7720 cm&lt;sup&gt;2&lt;/sup&gt;/Vs and sheet carrier concentration of 3.3&#215;10&lt;sup&gt;12&lt;/sup&gt; cm&lt;sup&gt;-22&lt;/sup&gt;, utilise a Pt gate, a high-k dielectric (k&#8776;20), and a &#948;-doped InAlAs/InGaAs/InAlAs heterostructure. The devices have a typical maximum drive current (I&lt;sub&gt;d,sat&lt;/sub&gt;) of 933 &#956;A/&#956;m, extrinsic transconductance (g&lt;sub&gt;m&lt;/sub&gt;) of 737 &#956;S/&#956;m, gate leakage (I&lt;sub&gt;g&lt;/sub&gt;) of 40 pA, and on-resistance (R&lt;sub&gt;on&lt;/sub&gt;) of 555 &#937;&#956;m. The g&lt;sub&gt;m&lt;/sub&gt; and R&lt;sub&gt;on&lt;/sub&gt; figures of merit are the best reported to date for any III-V MOSFET

    High Mobility III-V MOSFETs For RF and Digital Applications

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    Developments over the last 15 years in the areas of materials and devices have finally delivered competitive III-V MOSFETs with high mobility channels. This paper briefly reviews the above developments, discusses properties of the GdGaO/Ga2O3 MOS systems, presents GaAs MOSFET DC and RF data, and concludes with an outlook for high indium content channel MOSFETs. GaAs based MOSFETs are potentially suitable for RF power amplification, switching, and front-end integration in mobile and wireless applications while MOSFETs with high indium content channels are of interest for future CMOS applications

    Last interglacial reef limestones, northeastern St. Croix, US Virgin Islands-evidence of tectonic tilting and subsidence since MIS 5.5

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    Most last interglacial (MIS 5.5) coral reef deposits in the Caribbean are emergent. However, in St. Croix, these are found mainly at depth, underneath Holocene material and confirmed by TIMS U-Th dated corals from eight cores through Holocene reefs. The only emergent MIS 5.5 marine deposit peaks at +1.5 m MSL at the northwestern end of the island. The Late Pleistocene surface decreases at least 9.25 m (based on reef crest elevations) in elevation over 15 km along a 0.62 m/km eastward (alongshore) slope. Neither differential erosion nor a naturally sloping deposit is likely, thus the directional elevation decrease requires the influence of tectonic processes. Platform tilting or differential subsidence increasing in rate to the east probably operated both during and since the last interglacial and created progressively greater accommodation space for increasingly thicker overlying Holocene reefs in an eastward direction. Rates of subsidence since MIS 5.5 increase from west to east, from 0.02 mm/year to 0.1 mm/year, assuming a MIS 5.5 +6-m sea level and +4 m initial reef elevation. St. Croix's association with extensional shelf faulting from the northern part of the Virgin Islands Basin, the Anegada Fault to the east and the Puerto Rico Trench to the north may be significant in terms of identifying mechanisms for, or past events resulting in, directional tilting. Identification of differential elevations of MIS 5.5 reefs adds substantially to the information on Late Quaternary tectonism of the area

    Resist residues and transistor gate fabrication

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    In this article, the authors investigate the formation and removal of resist residues with the main objective to improve the reliability of transistor gate fabrication. Device performance is strongly dependent on the quality of metal contacts and the interface between gate metal and substrates. Reliable transistor fabrication becomes increasingly difficult as transistor dimensions shrink. Residual resist layers can become significant if wet or dry etching steps are required for gate recessing, e.g., for high electron mobility transistors or the removal of thin oxide layers in III-V metal oxide semiconductor field effect transistor fabrication. They observe two sorts of residual resist layers in polymethyl methacrylate (PMMA): exposed and nonexposed. Exposed residuals have been observed by many groups in electron beam exposed and developed regions of PMMA. In this article, they show that the observed granularity lies on top of a continuous residual film and consider this effect on gate fabrication. They also present evidence of a nonexposed residual layer observed in regions of unexposed resist which have been subject to a standard solvent based resist strip and cleaning procedure. They further demonstrate that CV measurement techniques can be used to detect the presence of residual layers of resist
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