Matching Level And Investors’ Heterogeneous Beliefs

This study investigated the relation between matching level and investors’ heterogeneous beliefs using listed firm (KOSPI) data in Korea. This study is based on prior research that reported that the higher the matching level, the less the noise included in accounting earnings and the higher the earnings quality. Karpoff (1986), Bamber (1987), Ajinkya, Atiase, & Gift (1991) and Dormeier (2011) explain that if there are different interpretations among investors regarding intrinsic value of a company, as a result, the trading volume can represent investors’ heterogeneous beliefs. Whereas the previous studies on matching level analyzed what kind of impact matching level improvement has on earnings quality, accumulated market adjusted return, foreign ownership, future earnings response coefficient (FERC) and bond credit rating. However, these studies have problems in measuring the matching level. So this study suggested additional proxy on matching level in addition to the proxy used in previous studies. Specifically, we analyzed the matching level model of Paek’s (2011b) by using the Prais-Winsten estimation method and then used the calculated explanatory power (Adj.R2) as a proxy for the additional matching level. To empirically analyze hypothesis of this study, we used firm-year observation from 4,094 firms listed on Korean Stock Exchange over the period from 2003 to 2011. We found that matching level regression coefficient consistently showed significantly negative values for each measurement. Moreover, we analyzed additionally by measuring the calculated regression coefficient (?2) of current expenses as matching level response coefficient after analyzing Dichev and Tang’s (2008) matching level measuring model by Prais-Winsten estimation method. It showed that regression coefficient of the current expenses and trading volume have negative correlation. This is consistent with this study, and it can be analyzed that as matching level improves, investors’ heterogeneous beliefs decrease. According to microeconomics theory of Mas-Colell, Whinston, and Green (1995), trading volume is explained to affect price changes. However, accounting and related studies analyze the information effect by using price change only. In this sense, this study is meaningful in that it conducted an analysis on the information effect of matching level through trading volume. In addition, this study contributes to understand the microscopic structure of the capital market

Measuring national capability over big science's multidisciplinarity: A case study of nuclear fusion research

In the era of big science, countries allocate big research and development budgets to large scientific facilities that boost collaboration and research capability. A nuclear fusion device called the "tokamak" is a source of great interest for many countries because it ideally generates sustainable energy expected to solve the energy crisis in the future. Here, to explore the scientific effects of tokamaks, we map a country's research capability in nuclear fusion research with normalized revealed comparative advantage on five topical clusters-material, plasma, device, diagnostics, and simulation-detected through a dynamic topic model. Our approach captures not only the growth of China, India, and the Republic of Korea but also the decline of Canada, Japan, Sweden, and the Netherlands. Time points of their rise and fall are related to tokamak operation, highlighting the importance of large facilities in big science. The gravity model points out that two countries collaborate less in device, diagnostics, and plasma research if they have comparative advantages in different topics. This relation is a unique feature of nuclear fusion compared to other science fields. Our results can be used and extended when building national policies for big science.11Yscopu

Efficient Hardware Controller Synthesis for Synchronous Dataflow Graph in System Level Design

Abstract—This paper concerns automatic hardware synthesis from data flow graph (DFG) specification in system level design. In the presented design methodology, each node of a data flow graph represents a hardware library module that contains a synthesizable VHDL code. Our proposed technique automatically synthesizes a clever control structure, cascaded counter controller, that supports asynchronous interaction with outside modules while efficiently implementing the synchronous dataflow semantics of the graph at the same time. Through comparison with previous works with some examples, the novelty of the proposed technique is demonstrated.This work was supported by the National Research Laboratory (NRL) Grant and the Brain Korea 21 Project. The RIACT at Seoul National University provides research facilities for this study

Hardware Synthesis From Coarse-Grained Dataflow Specification For Fast HW/SW Cosynthesis

This paper concerns automatic hardware synthesis from data flow graph (DFG) specification for fast HW/SW cosynthesis. A node in DFG represents a coarse grain block such as FIR and DCT and a port in a block may consume multiple data samples per invocation, which distinguishes our approach from behavioral synthesis and complicates the problem. In the presented design methodology, a dataflow graph with specified algorithm can be mapped to various hardware structures according to the resource allocation and schedule information. This simplifies the management of the area/performance tradeoff in hardware design and widens the design space of hardware implementation of a dataflow graph compared with the previous approaches. Through experiments with some examples, the usefulness of the proposed technique is demonstrated

Bibliometric Analysis of Collaboration Network and the Role of Research Station in Antarctic Science

Due to the large scale of Antarctic science, scientific collaboration is required for conducting scientific research. In this study, we attempted to investigate collaboration network and the role of research station in Antarctic science based on bibliometric data from 1995 to 2014. We confirmed that geographical proximity tends to be important for scientific collaboration by employing community detection in the network. This result raises the question about what the role of research station in Antarctica is. We tried to reveal its role by focusing on five countries, Belgium, China, Czech Republic, India, and Korea that constructed new research stations during the last decade. Relative growth rate, a value to measure the growth of publications, didn't differ much around the construction period compared to those in other periods for these countries except Belgium. However, we found eographical keywords emerged around the construction for all five countries. These keywords were utilized to observe national research activities in Antarctica. They show where countries started to be concerned about after the construction.11Nscopuskc

Does Pitch Type - Zone Uncertainty Matter to a Pitcher's Performance?

Baseball is a game of numbers. Large-scale baseball data have been utilized in decision making process by team managers. Recent studies with PITCHf/x, a system that tracks every pitch, provide new insights on the role of the pitch-type sequence in the pitcher’s performance. These studies are based on the assumption that the pitch-type uncertainty puts the hitter at a disadvantage. However, the pitch-zone uncertainty, another factor of pitching uncertainty, is neglected in many cases. Here, we introduce normalized mutual information for pitch type and pitch-zone as an indicator of pitching uncertainty. A pitcher with less of a repertoire with respect to type-zone combination has high normalized mutual information in pitching. We calculate the pitch type - zone uncertainties for major league baseball starting pitchers and compare the results with field independent pitching, a metric of pitcher’s performance. Our analysis shows that normalized mutual information is uncorrelated with performance in nine distinct subgroups extracted from revealed comparative advantage in pitch type. This result underlines the importance of the pitcher’s repertoire and ability to be competitive in professional baseball.11Nscopuskc

Optimized RTL Code Generation from Coarse-Grain Dataflow Specification for Fast HW/SW Cosynthesis

This paper presents a new methodology of automatic RTL code generation from coarse-grain dataflow specification for fast HW/SW cosynthesis. A node in a coarse-grain dataflow specification represents a functional block such as FIR and DCT and an arc may deliver multiple data samples per block invocation, which complicates the problem and distinguishes it from behavioral synthesis problem. Given optimized HW library blocks for dataflow nodes, we aim to generate the RTL codes for the entire hardware system including glue logics such as buffer and MUX, and the central controller. In the proposed design methodology, a dataflow graph can be mapped to various hardware structures by changing the resource allocation and schedule information. It simplifies the management of the area/performance tradeoff in hardware design and widens the design space of hardware implementation of a dataflow graph. We also support Fractional Rate Dataflow (FRDF) specification for more efficient hardware implementation. To overcome the additional hardware area overhead in the synthesized architecture, we propose two techniques reducing buffer overhead. Through experiments with some real examples, the usefulness of the proposed technique is demonstrated.This work was supported by Brain Korea 21 project, SystemIC 2010 project funded by Korean MOCIE, and KOSEF research program (R17-2007-086- 01001-0). This work was also partly sponsored by ETRI SoC Industry Promotion Center, Human Resource Development Project for IT SoC Architect. The ICT and ISRC at Seoul National University and IDEC provided research facilities for this study

Optimized RTL Code Generation from Coarse-Grain Dataflow Specification for Fast HW/SW Cosynthesis

This paper presents a new methodology of automatic RTL code generation from coarse-grain dataflow specification for fast HW/SW cosynthesis. A node in a coarse-grain dataflow specification represents a functional block such as FIR and DCT and an arc may deliver multiple data samples per block invocation, which complicates the problem and distinguishes it from behavioral synthesis problem. Given optimized HW library blocks for dataflow nodes, we aim to generate the RTL codes for the entire hardware system including glue logics such as buffer and MUX, and the central controller. In the proposed design methodology, a dataflow graph can be mapped to various hardware structures by changing the resource allocation and schedule information. It simplifies the management of the area/performance tradeoff in hardware design and widens the design space of hardware implementation of a dataflow graph. We also support Fractional Rate Dataflow (FRDF) specification for more efficient hardware implementation. To overcome the additional hardware area overhead in the synthesized architecture, we propose two techniques reducing buffer overhead. Through experiments with some real examples, the usefulness of the proposed technique is demonstrated