APLYSIE : un circuit neuro-mimétique : réalisation et intégration sur tranche

Un algorithme récurrent de la phase de reconnaissance d'un réseau mono couches de Hopfield a été implante. Le problème lie à l'interconnexion complète des neurones a été implantée sur une architecture systolique 2d ou chaque processeur représente une interaction neurone/neurone. Un circuit intégré de 16 neurones, soit 256 synapses, a été réalisé en technologie CMOS. Un tel circuit permet d'effectuer plus d'un demi milliard d'opérations synaptiques par second

Aplysie : un circuit neuro-mimetique : realisation et integration sur tranche

SIGLECNRS T Bordereau / INIST-CNRS - Institut de l'Information Scientifique et TechniqueFRFranc

Managing variability in 40NM and 28NM designs

This article presents a study of variability-aware design methodology that allows designers to lower the risks of silicon failure and to improve their design margins and flows. Supplied by a group of researchers and engineers at CSR, the University of Southampton and Cadence Design Systems

Analysis, quantification, and mitigation of electrical variability due to layout dependent effects in SOC designs

Variability in performance and power of 40nm and 28nm CMOS cells is highly dependent on the context in which the cells are used. In this study, the effects of context on a number of clock tree cells from standard cell libraries have been investigated. The study also demonstrated how the Litho Electrical Analyzer (LEA) tool from Cadence is used to analyze the context-dependent variability. During the study, it was observed that the device characteristics including Vth, Idsat, and Ioff are significantly affected by Layout Dependent Effects (LDE), resulting in variability of performance and power of standard cells. Moreover, the dummy diffusions acting as mitigation process offered limited improvement for the effects of context. On the other hand, the cell level variability due to stress was analyzed. So, it is suggested that the relative variability of a cell is determined by its size and structure, and the variability can be improved to some extent by editing the cells' structure. Based on the analysis of the physical sources and properties of LDE, this paper presents a set of layout guidelines for mitigating layout dependent variability of 40 and 28nm CMOS cell