The VolumePro Real-Time Ray-Casting System

This paper describes VolumePro, the world’s first single-chip realtime volume rendering system for consumer PCs. VolumePro implements ray-casting with parallel slice-by-slice processing. Our discussion of the architecture focuses mainly on the rendering pipeline and the memory organization. VolumePro has hardware for gradient estimation, classification, and per-sample Phong illumination. The system does not perform any pre-processing and makes parameter adjustments and changes to the volume data immediately visible. We describe several advanced features of VolumePro, such as gradient magnitude modulation of opacity and illumination, supersampling, cropping and cut planes. The system renders 500 million interpolated, Phong illuminated, composited samples per second. This is sufficient to render volumes with up to 16 million voxels (e.g., 2563) at 30 frames per second.Engineering and Applied Science

A Parallel Pipeline Convolution for Perspective Projection in Real-Time Volume Rendering

This paper describes a convolution with a systolic array structure for perspective projection in real-time volume graphics based on the shear-warp method. In the original method, the further the ray proceeds, the more voxels are required to calculate the convolution. The increase in required voxels makes it difficult to implement the method in a VLSI-oriented architecture. We implement a 3D convolution using three serial 1D convolutions along the X, Y, and Z axes, which reduces the number of calculation units from M3 to 3M, where the convolution is calculated for the M3 area. The number of pipelines for the rays is V2 for V3 voxel datasets. If the hardware of a single pipeline can calculate the V rays, then each of the implemented pipelines is assigned to V theoretical pipelines (for V2 rays). The number of hardware pipelines should be much smaller than V theoretical pipelines in actual implementation. We folded the theoretical pipelines and reduced them to a certain number of hardware pipelines. We examined the relation between the folding process and its necessary time delay. The architecture can generate an image of a 2563 voxel dataset (V=256) at 30Hz with four pipelines. In addition, the architecture can be extended easily for 5123 (V=512) and 10243 (V=1024) datasets, with 32 pipelines and 256 pipelines. Our architecture has processing scalability.Engineering and Applied Science

EM-Cube: An Architecture for Low-Cost Real-Time Volume Rendering

EM-Cube is a VLSI architecture for low-cost, high quality volume rendering at full video frame rates. Derived from the Cube-4 architecture developed at SUNY at Stony Brook, EM-Cube computes sample points and gradients on-the-fly to project 3-dimensional volume data onto 2-dimensional images with realistic lighting and shading. A modest rendering system based on EM-Cube consists of a PCI card with four rendering chips (ASICs), four 64Mbit SDRAMs to hold the volume data, and four SRAMs to capture the rendered image. The performance target for this configuration is to render images from a 256^3 x 16 bit data set at 30 frames/sec. The EM-Cube architecture can be scaled to larger volume data-sets and/or higher frame rates by adding additional ASICs, SDRAMs, and SRAMs. This paper addresses three major challenges encountered developing EM-Cube into a practical product: exploiting the bandwidth inherent in the SDRAMs containing the volume data, keeping the pin-count between adjacent ASICs at a tractable level, and reducing the on-chip storage required to hold the intermediate results of rendering.Engineering and Applied Science

Buffering in an ATM Local Area Network With Real Time Channels

Traffic in local area networks is characterized by considerable ¨burstiness ¨ , even traffic representing continuous data types such as audio or video which require real-time network guarantees. Existing algorithms for implementing real-time channels assume large or unlimited buffer space in network switches in order to buffer entire messages. However, such large buffers also imply large worst-case delays and high jitter. An alternative approach in an ATM network is to move the buffering to the client interface and to transmit cells of a real-time channel more uniformly. This allows the network to guarantee tighter deadlines and less jitter and to reduce the amount of reserved buffer space required to support the real-time channels at each switch. It is argued that this is practical in local area networks, even when it is not always practical in wider area networks

On the Duality of Rate-based and Credit-based Flow Control

Two forms of flow control for ATM (Asynchronous Transfer Mode) networks are examined, namely rate-based and credit-based flow control of ABR (Available Bit Rate) traffic. Under certain assumptions, these two are shown to be duals of each other. That is, the average traffic flow of a rate-based network can be achieved by controlling buffer space of a credit-based network. Similarly, the buffer requirements of a credit- based network can be achieved by controlling the rates in a rate-based network. Using the duality, it can be shown that several claimed advantages- in which some feature or attribute is claimed to be available in one form of flow control but not the other- are not advantages at all and, in fact, have corresponding implementations in the other. However, the duality is not perfect, and some asymmetries remain between these two forms of flow control. Some observations are offered to reduce the differences between these in practical networks. ACM SIGCOMM ‘95 Conferenc

A General Purpose Queue Architecture for an ATM Switch

republishing for any other purpose shall require a license with payment of fee to Mitsubishi Electric Research Laboratories. All rights reserved. Copyright Mitsubishi Electric Research Laboratories, Inc., 1994 201 Broadway, Cambridge, Massachusetts 02139 Revision History:--- 1. First version: July 28, 1994 2. Revised September 30, 1994 A General Purpose Queue Architecture for an ATM Switch Hugh C. Lauer, Abhijit Ghosh, 201 Broadway Cambridge, MA 02139 both real-time and non-real-time communication. The central part of the architecture is a kind of searchable, self-timed FIFO circuit into which are merged the queues of all virtual channels in the switch. Arriving cells are tagged with numerical values indicating the priorities, deadlines, or other characterizations of the order of transmission, then they are inserted into the queue. Entries are selected from the queue both by destination and by tag, with the earliest entry being selected from among a set of equals. By th

Corporation Palo Alto,

Many operating system designs can be placed into one of two very rough categories, depending upon how they implement and use the notions of process an