Stress-Induced Leakage Current in p+ Poly MOS Capacitors with Poly-Si and Poly-Si0.7Ge0.3 Gate Material

The gate bias polarity dependence of stress-induced leakage current (SILC) of PMOS capacitors with a p+ polycrystalline silicon (poly-Si) and polycrystalline Silicon-Germanium (poly-Si0.7 Ge0.3) gate on 5.6-nm thick gate oxides has been investigated. It is shown that the SILC characteristics are highly asymmetric with gate bias polarity. This asymmetric behavior is explained by the occurrence of a different injection mechanism for negative bias, compared to positive bias where Fowler-Nordheim (FN) tunneling is the main conduction mechanism. For gate injection, a larger oxide field is required to obtain the same tunneling current, which leads to reduced SILC at low fields. Moreover, at negative gate bias, the higher valence band position of poly-SiGe compared to poly-Si reduces the barrier height for tunneling to traps and hence leads to increased SILC. At positive gate bias, reduced SILC is observed for poly-SiGe gates compared to poly-Si gates. This is most likely due to a lower concentration of Boron in the dielectric in the case of poly-SiGe compared to poly-Si. This makes Boron-doped poly-SiGe a very interesting gate material for nonvolatile memory device

Minority Carrier Tunneling and Stress-Induced Leakage Current for p+ gate MOS Capacitors with Poly-Si and PolySi0.7Ge0.3 Gate Material

In this paper the I-V conduction mechanism for gate injection (-V g), Stress-Induced Leakage Current (SILC) characteristics and time-to-breakdown (tbd) of PMOS capacitors with p+-poly-Si and poly-SiGe gate material on 5.6, 4.8 and 3.1 nm oxide thickness are studied. A model based on Minority Carrier Tunneling (MCT) from the gate is proposed for the I-V and SILC characteristics at -Vg of our devices. Time-to-breakdown data are presented and discusse

Visible light emission from reverse-biased silicon nanometer-scale diode-antifuses

Silicon nanometer-scale diodes have been fabricated to emit light in the visible range at low power consumption. Such structures are candidates for emitter elements in Si-based optical interconnect schemes. Spectral measurements of Electroluminescence (EL) on the reverse-biased nanometer-scale diodes brought into breakdown have been carried out over the photon energy range of 1.4-2.8 eV. Previously proposed mechanisms for avalanche emission from conventional silicon p-n junctions are discussed in order to understand the origin of the emission. Also the stability of the diodes has been tested. Results indicate that our nanometer-scale diodes are basically high quality devices. Furthermore due to the nanometer-scale dimensions, very high electrical fields and current densities are possible at low power consumption. This makes these diodes an excellent candidate to be utilized as a light source in Si-based sensors and actuator application

Temperature Acceleration of Thin Gate-Oxide Degradation

The temperature dependence of TBD and QBD of ultra-thin (3.9 nm thick) gate oxides was studied for p+-poly Si PMOS and n+-poly Si NMOS capacitors. It was observed that the temperature acceleration of TBD exhibits a non-Arrhenius behavior, meaning that no activation energy could be determined. Furthermore for p+ gate devices both TBD and QBD exhibit a stronger temperature dependence compared to n+ poly-Si MOS devices. Also the dependence on the gate voltage is much stronger. This might have consequences for the reliability of p+ gate devices under operating conditions

SILC in MOS capacitors with poly-Si and poly-Si0.7Ge0.3 gate material

In this paper the DC-SILC characteristics of n+ and p+ poly-Si and poly-SiGe MOS capacitors are studied for substrate(+Vg) and gate-injection(−Vg) conditions. P+ and n+-gates with poly silicon (poly-Si) and poly Silicon-Germanium (poly Si−0.7Ge0.3) were used to study the influence of the gate workfunction on gate current and SILC currents. For n+ poly-SiGe, reduced poly depletion and no significant difference in SILC characteristics compared to n+ poly-Si gate devices is observed. For p+ gate devices asymmetric SILC and reduced SILC for poly-SiGe is observed