Optimization of Dynamic Range of Cascade Filter Realization

This paper deals with a dynamic range optimization procedure for active filters based on the cascade realization. Dynamic characteristics of the cascade filter depend on many factors, mainly on pole-zero pairing, section ordering and gain assignment. Just the procedure for an optimal gain assignment for particular biquadratic sections is discussed in this paper. The input parameters of the procedure are parameters of particular biquads i.e. pole frequency ω0, quality factor Q, eventually zero frequency ωn for elliptic section and the transfer function type of the section. The gain is distributed so that output signal limitation of particular biquads occurs for the same level of the filter input signal. The procedure is versatile - can be used for analog as well as for digital filters with the cascade structure. The presented algorithm is fully universal (does not suppose any simplification). It has been used in Syntfil package for the filter design in the mathematical program Maple

Implementation of a Two-Channel Maximally Decimated Filter Bank using Switched Capacitor Circuits

The aim of this paper is to describe the implementation of a two-channel filter bank (FB) using the switched capacitor (SC) technique considering real properties of operational amplifiers (OpAmps). The design procedure is presented and key recommendations for the implementation are given. The implementation procedure describes the design of two-channel filter bank using an IIR Cauer filter, conversion of IIR into the SC filters and the final implementation of the SC filters. The whole design and an SC circuit implementation is performed by a PraCAn package in Maple. To verify the whole filter bank, resulting real property circuit structures are completely simulated by WinSpice and ELDO simulators. The results confirm that perfect reconstruction conditions can be almost accepted for the filter bank implemented by the SC circuits. The phase response of the SC filter bank is not strictly linear due to the IIR filters. However, the final ripple of a magnitude frequency response in the passband is almost constant, app. 0.5 dB for a real circuit analysis

Design of Dual Bandpass and Bandreject LC Ladder Filters

This paper deals with the design of two-passband bandpass and two-stopband bandreject LC ladder filters. The design method is based on the special dual frequency transformation that transforms normalized lowpass to either bandpass with two passbands or to bandreject with two stopbands that are specified by four cutoff frequencies. The paper shows analytical solution relating these four cutoff frequencies to parameters of dual frequency transformation. It enables a direct computation of dual band LC filter elements from a normalized lowpass filter by means of simple relations. These relations have been implemented in the mathematical program Maple (TM) as new user functions. They are supposed to be used as an enhancement of Syntfil package which is intended for analog filter design in program Maple. Specific application is shown on an example of the two-passband bandpass LC filter design

Developing Model-Based Design Evaluation for Pipelined A/D Converters

This paper deals with a prospective approach of modeling, design evaluation and error determination applied to pipelined A/D converter architecture. In contrast with conventional ADC modeling algorithms targeted to extract the maximum ADC non-linearity error, the innovative approach presented allows to decompose magnitudes of individual error sources from a measured or simulated response of an ADC device. Design Evaluation methodology was successfully applied to Nyquist rate cyclic converters in our works [13]. Now, we extend its principles to pipelined architecture. This qualitative decomposition can significantly contribute to the ADC calibration procedure performed on the production line in term of integral and differential nonlinearity. This is backgrounded by the fact that the knowledge of ADC performance contributors provided by the proposed method helps to adjust the values of on-chip converter components so as to equalize (and possibly minimize) the total non-linearity error. In this paper, the design evaluation procedure is demonstrated on a system design example of pipelined A/D converter. Significant simulation results of each stage of the design evaluation process are given, starting from the INL performance extraction proceeded in a powerful Virtual Testing Environment implemented in Maple™ software and finishing by an error source simulation, modeling of pipelined ADC structure and determination of error source contribution, suitable for a generic process flow

High Voltage Coil Current Sensor for DC-DC Converters Employing DDCC

Current sensor is an integral part of every switching converter. It is used for over-current protection, regulation and in case of multiphase converters for balancing. A new high voltage current sensor for coil-based current sensing in DC-DC converters is presented. The sensor employs DDCC with high voltage input stage and gain trimming. The circuit has been simulated and implemented in 0.35 um BCD technology as part of a multiphase DC-DC converter where its function has been verified. The circuit is able to sustain common mode voltage on the input up to 40 V, it occupies 0.387*0.345 mm2 and consumes 3.2 mW typically

Analysis and Synthesis of the Digital Structures by the Matrix Method

This paper presents a general matrix algorithm for analysis of digital filters. The method proposed in this paper allows not only the analysis of the digital filters, but also the construction of new structures of the canonic or non-canonic digital filter. Equivalent filters of different structures can be found according to various matrix expansions. The structures can be calculated even from transfer function or from state-space matrices and with the additional advantage of requiring minimum number of shifting elements. Traditional research methods are not able to construct the system with a minimum of the shifting operations

Guidelines on the Switch Transistors Sizing Using the Symbolic Description for the Cross-Coupled Charge Pump

This paper presents a symbolic description of the design process of the switch transistors for the cross- coupled charge pump applications. Discrete-time analog circuits are usually designed by the numerical algorithms in the professional simulator software which can be an extremely time-consuming process in contrast to described analytical procedure. The significant part of the pumping losses is caused by the reverse current through the switch transistors due to continuous-time voltage change on the main capacitors. Design process is based on the analytical expression of the time response characteristics of the pump stage as an analog system with using BSIM model equations. The main benefit of the article is the analytical transistors sizing formula, so that the maximum voltage gain is achieved. The diode transistor is dimensioned for the pump requirements, as the maximal pump output ripple voltage, current, etc. The characteristics of the proposed circuit has been verified by simulation in ELDO Spice. Results are valid for N-stage charge pump and also applicable for other model equations as PSP, EKV

Triangle/Square Waveform Generator Using Area Efficient Hysteresis Comparator

A function generator generating both square and triangle waveforms is proposed. The generator employs only one low area comparator with accurate hysteresis set by a bias current and a resistor. Oscillation frequency and its non-idealities are analyzed. The function of the proposed circuit is demonstrated on a design of 1 MHz oscillator in STMicroelectronics 180 nm BCD technology. The designed circuit is thoroughly simulated including trimming evaluation. It consumes 4.1 μA at 1.8 V and takes 0.0126 mm2 of silicon area. The temperature variation from -40°C to 125°C is ±1.5 % and the temperature coefficient is 127 ppm/°C

Triangle/Square Waveform Generator Using Area Efficient Hysteresis Comparator

A function generator generating both square and triangle waveforms is proposed. The generator employs only one low area comparator with accurate hysteresis set by a bias current and a resistor. Oscillation frequency and its non-idealities are analyzed. The function of the proposed circuit is demonstrated on a design of 1 MHz oscillator in STMicroelectronics 180 nm BCD technology. The designed circuit is thoroughly simulated including trimming evaluation. It consumes 4.1 μA at 1.8 V and takes 0.0126 mm2 of silicon area. The temperature variation from -40°C to 125°C is ±1.5 % and the temperature coefficient is 127 ppm/°C

High Voltage Coil Current Sensor for DC-DC Converters Employing DDCC

Current sensor is an integral part of every switching converter. It is used for over-current protection, regulation and in case of multiphase converters for balancing. A new high voltage current sensor for coil-based current sensing in DC-DC converters is presented. The sensor employs DDCC with high voltage input stage and gain trimming. The circuit has been simulated and implemented in 0.35 um BCD technology as part of a multiphase DC-DC converter where its function has been verified. The circuit is able to sustain common mode voltage on the input up to 40 V, it occupies 0.387*0.345 mm2 and consumes 3.2 mW typically