Patient-related post-ERCP pancreatitis (PEP) risk factors between two groups of patients: Prophylactic pancreatic stent and rectal indomethacin

Background: Pancreatitis is one of the most crucial complications following endoscopic retrograde cholangiopancreatography (ERCP). The purpose of the current study was to investigate patient-related post-ERCP pancreatitis (PEP) risk factors in two groups of patients: prophylactic pancreatic stent and rectal indomethacin. Methods: Two different prophylactic modalities were planned and complications were assessed based on the defined inclusion criteria. In this study, the patients were evaluated for the procedure and patient-related risk factors in post-ERCP pancreatitis in the recipient groups of the prophylactic pancreatic stent and rectal indomethacin. Results: Pancreatitis was confirmed in 27 of all 170 selected patients after ERCP. By univariate analysis, two variables were significant with the development of PEP. Regarding the patient-related risk factors, unique subjects with common bile duct (CBD) dilated 10mm were more exposed to an increased chance of PEP (P=0. 015); meanwhile, other factors did not correlate with the increased possibility of PEP in both groups. The only procedure-related risk factor for PEP was the deep cannulation of the pancreatic duct in both groups during the procedure with an incremental significant incidence of pancreatitis (P=0.005). Comparison of prophylactic pancreatic stent and rectal indomethacin showed no effects in term of post ERCP pancreatitis reduction. Additionally, there was no significant difference between these two strategies in the rate of PEP. Conclusion: Prophylactic pancreatic duct stents and administration of rectal indomethacin cannot have particular approaches for reducing the possible occurrence of PEP. The increase in time of deep cannulation and the presence of CBD dilation <10mm could be considered as important risk factors. &#160

A Reconfigurable Fabric for Accelerating Large-Scale Datacenter Services

Datacenter workloads demand high computational capabilities, flexibility, power efficiency, and low cost. It is challenging to improve all of these factors simultaneously. To advance datacenter capabilities beyond what commodity server designs can provide, we designed and built a composable, reconfigurable hardware fabric based on field programmable gate arrays (FPGA). Each server in the fabric contains one FPGA, and all FPGAs within a 48-server rack are interconnected over a low-latency, high-bandwidth network. We describe a medium-scale deployment of this fabric on a bed of 1632 servers, and measure its effectiveness in accelerating the ranking component of the Bing web search engine. We describe the requirements and architecture of the system, detail the critical engineering challenges and solutions needed to make the system robust in the presence of failures, and measure the performance, power, and resilience of the system. Under high load, the large-scale reconfigurable fabric improves the ranking throughput of each server by 95% at a desirable latency distribution or reduces tail latency by 29% at a fixed throughput. In other words, the reconfigurable fabric enables the same throughput using only half the number of servers

Compiling Stream Applications for Heterogeneous Architectures.

Heterogeneous processing systems have become the industry standard in almost every segment of the computing market from servers to mobile systems. In addition to employing shared/distributed memory processors, the current trend is to use hardware components such as field programmable gate arrays (FPGAs), single instruction multiple data (SIMD) engines and graphics processing units (GPUs) in heterogeneous systems. As a result of this trend, extracting maximum performance requires compilation to highly heterogeneous architectures that include parts with different memory and computation models. Although there has been significant amount of research on programing each of these architectures individually, targeting a heterogeneous system without specializing an application to each component separately is still an open problem. Besides performance, the portability of an application between different pieces of a system and retargetability to various heterogeneous architectures is a significant challenge for programmers. To efficiently exploit the heterogeneity, it is necessary to have a programming model that provides a higher-level of abstraction to the programmer and the related compilation framework. In this thesis, we first focus on enabling a write-once programming paradigm in the context of the stream programming model for various components of heterogeneous systems. We mainly focus on FPGAs, SIMD engines and GPUs as these architectures will play an important role in accelerating various parts of applications on heterogeneous systems. We introduce several compiler optimizations that facilitate portability and retargetability while achieving high performance. As a result of our compilation system, programmers can write a program once and efficiently run it on different components of a system. Second, we focus on an important challenge that arises in heterogeneous systems when there are dynamic resource changes. The ability to dynamically adapt a running application to a target architecture in the face of changes in resource availability (e.g., number of cores, available memory or bandwidth) is crucial to a wider adoption of heterogeneous architectures. In this work, we introduce a hybrid flexible compilation framework that facilitates dynamic adaption of applications to the changing characteristics of the underlying architecture.Ph.D.Computer Science & EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/86537/1/hormati_1.pd

Exploiting Narrow Accelerators with Data-Centric Subgraph Mapping

The demand for high performance has driven acyclic computation accelerators into extensive use in modern embedded and desktop architectures. Accelerators that are ideal from a software perspective, are difficult or impossible to integrate in many modern architectures, though, due to area and timing requirements. This reality is coupled with the observation that many application domains under-utilize accelerator hardware, because of the narrow data they operate on and the nature of their computation. In this work, we take advantage of these facts to design accelerators capable of executing in modern architectures by narrowing datapath width and reducing interconnect. Novel compiler techniques are developed in order to generate highquality code for the reduced-cost accelerators and prevent performance loss to the extent possible. First, data width profiling is used to statistically determine how wide program data will be at run time. This information is used by the subgraph mapping algorithm to optimally select subgraphs for execution on targeted narrow accelerators. Overall, our data-centric compilation techniques achieve on average 6.5%, and up to 12%, speed up over previous subgraph mapping algorithms for 8-bit accelerators. We also show that, with appropriate compiler support, the increase in the total number of execution cycles in reduced-interconnect accelerators is less than 1 % of the fully-connected accelerator. 1

Sponge: Portable stream programming on graphics engines

Graphics processing units (GPUs) provide a low cost platform for accelerating high performance computations. The introduction of new programming languages, such as CUDA and OpenCL, makes GPU programming attractive to a wide variety of programmers. However, programming GPUs is still a cumbersome task for two primary reasons: tedious performance optimizations and lack of portability. First, optimizing an algorithm for a specific GPU is a time-consuming task that requires a thorough understanding of both the algorithm and the underlying hardware. Unoptimized CUDA programs typically only achieve a small fraction of the peak GPU performance. Second, GPU code lacks efficient portability as code written for one GPU can be inefficient when executed on another. Moving code from one GPU to another while maintaining the desired performance is a non-trivial task often requiring significant modifications to account for the hardware differences. In this work, we propose Sponge, a compilation framework for GPUs using synchronous data flow streaming languages. Sponge is capable of performing a wide variety of optimizations to generate efficient code for graphics engines. Sponge alleviates the problems associated with current GPU programming methods by providing portability across different generations of GPUs and CPUs, and a better abstraction of the hardware details, such as the memory hierarchy and threading model. Using streaming, we provide a writeonce software paradigm and rely on the compiler to automatically create optimized CUDA code for a wide variety of GPU targets. Sponge’s compiler optimizations improve the performance of the baseline CUDA implementations by an average of 3.2x

Liquid Metal: object-oriented programming across the hardware/software boundary

Abstract. The paradigm shift in processor design from monolithic processors to multicore has renewed interest in programming models that facilitate parallelism. While multicores are here today, the future is likely to witness architectures that use reconfigurable fabrics (FPGAs) as coprocessors. FPGAs provide an unmatched ability to tailor their circuitry per application, leading to better performance at lower power. Unfortunately, the skills required to program FPGAs are beyond the expertise of skilled software programmers. This paper shows how to bridge the gap between programming software vs. hardware. We introduce Lime, a new Object-Oriented language that can be compiled for the JVM or into a synthesizable hardware description language. Lime extends Java with features that provide a way to carry OO concepts into efficient hardware. We detail an end-to-end system from the language down to hardware synthesis and demonstrate a Lime program running on both a conventional processor and in an FPGA.