Compact solid-state CMOS single-photon detector array for in vivo NIR fluorescence lifetime oncology measurements

In near infrared fluorescence-guided surgical oncology, it is challenging to distinguish healthy from cancerous tissue. One promising research avenue consists in the analysis of the exogenous fluorophores’ lifetime, which are however in the (sub-)nanosecond range. We have integrated a single-photon pixel array, based on standard CMOS SPADs (single-photon avalanche diodes), in a compact, time-gated measurement system, named FluoCam. In vivo measurements were carried out with indocyanine green (ICG)-modified derivatives targeting the avb3 integrin, initially on a genetically engineered mouse model of melanoma injected with ICG conjugated with tetrameric cyclic pentapeptide (ICG􀀀E[c(RGDfK)4]), then on mice carrying tumour xenografts of U87-MG (a human primary glioblastoma cell line) injected with monomeric ICG􀀀c(RGDfK). Measurements on tumor, muscle and tail locations allowed us to demonstrate the feasibility of in vivo lifetime measurements with the FluoCam, to determine the characteristic lifetimes (around 500 ps) and subtle lifetime differences between bound and unbound ICG-modified fluorophores (10% level), as well as to estimate the available photon fluxes under realistic conditions

Cryo-CMOS for quantum computing, 2016 IEEE International Electron Devices Meeting (IEDM)

Cryogenic CMOS, or cryo-CMOS circuits and systems, are emerging in VLSI design for many applications, in primis quantum computing. Fault-tolerant quantum bits (qubits) in surface code configurations, one of the most accepted implementations in quantum computing, operate in deep sub-Kelvin regime and require scalable classical control circuits. In this paper we advocate the need for a new generation of deep-submicron CMOS circuits operating at deep-cryogenic temperatures to achieve the performance required in a fault-tolerant qubit system. We outline the challenges and limitations of operating CMOS in near-zero Kelvin regimes and we propose solutions. The paper concludes with several examples showing the suitability of integrating fault-tolerant.qubits with CMOS