Implementaion of a combined OFDM-demodulation and WCDMA-equalization module

For a dual-mode baseband receiver for the OFDMWireless LAN andWCDMA standards, integration of the demodulation and equalization tasks on a dedicated hardware module has been investigated. For OFDM demodulation, an FFT algorithm based on cascaded twiddle factor decomposition has been selected. This type of algorithm combines high spatial and tempo- ral regularity in the FFT data-flow graphs with a minimal number of computations. A frequency-domain algorithm based on a circulant channel approximation has been se- lected forWCDMA equalization. It has good performance, low hardware complexity and a low number of computa- tions. Its main advantage is the reuse of the FFT kernel, which contributes to the integration of both tasks. The demodulation and equalization module has been de- scribed at the register transfer level with the in-house developed Arx language. The core of the module is a pipelined radix-23 butterfly combined with a complex mul- tiplier and complex divider. The module has an area of 0.447 mm2 in 0.18 μm technology and a power consump- tion of 10.6 mW. The proposed module compares favorably with solutions reported in literature. Keywords—OFDMdemodulation,WCDMA, frequency- domain equalization, architecture design

Arx: A Toolset for the Efficient Simulation and Direct Synthesis of High-Performance Signal Processing Algorithms

This paper addresses the efficient implementation of highperformance signal-processing algorithms. In early stages of such designs many computation-intensive simulations may be necessary. This calls for hardware description formalisms targeted for efficient simulation (such as the programming language C). In current practice, other formalisms (such as VHDL) will often be used to map the design on hardware by means of logic synthesis. A manual, error-prone, translation of a description is then necessary. The line of thought of this paper is that the gap between simulation and synthesis should not be bridged by stretching the use of existing formalisms (e.g. defining a synthesizable subset of C), but by a language dedicated to an application domain. This resulted in Arx, which is meant for signal-processing hardware at the register-transfer level, either using floating-point or fixed-point data. Code generators with knowledge of the application domain then generate efficient simulation models and synthesizable VHDL. Several designers have already completed complex signal-processing designs using Arx in a short time, proving in practice that Arx is easy to learn. Benchmarks presented in this paper show that the generated simulation code is significantly faster than SystemC

RF performance of T-DAB receivers

In every wireless system, the weakest link determines the performance of the network. In this paper the Radio Frequency (RF) performance of both band III and L-band Terrestrial Digital Audio Broadcasting (T-DAB) consumer receivers are discussed. The receivers have been tested based on the EN 50248 standard. The test results show that the average consumer receiver for band III meets the requirements set by EN 50248, except for the non-adjacent interferer experiments. In this experiment, the average consumer receiver performs up to 10 dB worse than required. In addition, the experiments reveal that there is a large difference in performance between consumer receivers. Besides band III, also L-band consumer receivers have been evaluated. The results of the L-band experiments show that the consumer receivers are not capable of decoding a DAB signal with a COST207 rural area channel model in case of T-DAB mode IV. Network operators should for this reason use mode II for the L-band and should expect a larger influence of non-adjacent interference on receiver performance in band III than anticipated based on EN 50248