High Speed and Low Pedestal Error Bootstrapped CMOS Sample and Hold Circuit

A new high speed, low pedestal error bootstrapped CMOS sample and hold (S/H) circuit is proposed for high speed analog-to-digital converter (ADC). The proposed circuit is made up of CMOS transmission gate (TG) switch and two new bootstrap circuits for each transistor in TG switch. Both TG switch and bootstrap circuits are used to decrease channel charge injection and on-resistance input signal dependency. In result, distortion can be reduced. The decrease of channel charge injection input signal dependency also makes the minimizing of pedestal error by adjusting the width of NMOS and PMOS of TG switch possible. The performance of the proposed circuit was evaluated using HSPICE 0.18-m CMOS process. For 50 MHz sinusoidal 1 V peak-to-peak differential input signal with a 1 GHz sampling clock, the proposed circuit achieves 2.75 mV maximum pedestal error, 0.542 mW power consumption, 90.87 dB SNR, 73.50 SINAD which is equal to 11.92 bits ENOB, -73.58 dB THD, and 73.95 dB SFDR

Simple Measurement System for Biological Signal Using a Smartphone

This paper describes simple measurement system for biological signal using smartphone. The proposed system consists of an instrumentation amplifier, a filter and an AC/DC converter. The biological signal is converted to the digital data through the microphone terminal with A/D converter in the smartphone. In many cases, the circuits require the power sources such as the cell batteries, however, the proposed system is supplied the power through the earphone terminal of the smartphone. Therefore, the proposed system no require the batteries. The software of this system parallelizes the processing so that the earphone output and the microphone terminal can be executed at the same time. The proposed system was verified through the measurement of surface electromyogram using discrete parts and iOS. Results of experimentation, the proposed system was operating correctly

New active diode with bulk regulation transistors and its application to integrated voltage rectifier circuit

This paper describes new active diode with bulk regulation transistors and its application to the integrated voltage rectifier circuit for a biological signal measurement system with smartphone. The conventional active diode with BRT has the dead region which causes leak current, and the output voltages of the application (e.g. voltage rectifier circuit) decrease. In order to overcome these problem, we propose new active diode with BRT which uses the control signal from the comparator of active diode to eliminate the dead region. Next we apply the proposed active diode with BRT to the integrated voltage rectifier circuit. The proposed active diode with BRT and voltage rectifier circuit were fabricated using 0.6 μm standard CMOS process. From experimental results, the proposed active diode with BRT eliminates the dead region perfectly, and the proposed voltage rectifier circuit generates + 2.86 V (positive side) and - 2.70 V (negative side) under the condition that the amplitude and frequency of the input sinusoidal signal are 1.5 V and 10 kHz, respectively, and the load resistance is 10 kΩ

Proposal and design methodology of switching mode low dropout regulator for Bio-medical applications

The switching operation based low dropout (LDO) regulator utilizing on-off control is pre-sented. It consists of simple circuit elements which are comparator, some logic gates, switched capacitor and feedback circuit. In this study, we target the application to the power supply circuit for the analog front end (AFE) of bio-medical system (such as daily-used bio-monitoring devices) whose required maximum load current is 50 A. In this paper, the design procedure of the proposed LDO has been clarified and actual circuit design using the procedure has been done. The proposed LDO has been evaluated by SPICE simulation using 1P 2M 0.6 m CMOS process device parameters. From simulation results, we could confirm that the low quiescent current of 1 A with the output ripple of 5 mVpp. The circuit area is 0.0173 mm2 in spite of using 0.6 m design rules. The proposed circuit is suitable for adopting to the light load and low frequency applications

A Simple Transistors Width Adjustment Method on CMOS Transmission Gate Switch to Reduce Hold Error of S/H Circuit

Sample and Hold (S/H) circuit is one of the most important circuits in analog and mixed signal integrated circuit. This circuit is the main block of many applications, such as switched capacitor circuit, analog to digital converter (ADC), etc. The majority of S/H circuits are implemented using MOS technology because the high input impedance of MOS devices performs excellent holding functions. Ideal characteristics of the S/H circuit are low hold error, low On-resistance and constant On-resistance in all voltage levels. There are some techniques to reduce the hold error and achieve low On-resistance. However, these techniques need additional compensation circuit. For this reason, a simple transistors width adjustment method on CMOS transmission gate (TG) switch to reduce hold error of S/H circuit without additional circuit that can be implemented in the actual design process is proposed in this paper. The basic idea of the proposed method is balancing hold error caused by N-type and P-type MOS transistor in CMOS switch that is used in S/H circuit. The performance of the proposed method is evaluated using HSPICE with 0.6 µm CMOS standard process. As a result, using 1.5 V constant input in the PMOS transistor width WP range of 3 to 35 µm the average WN/WP ratio given by this proposed method is 0.928 with the average absolute hold error is 0.427 mV and maximum absolute hold error is 0.8 mV

CMOS Temperature Sensor with Programmable Temperature Range for Biomedical Applications

A CMOS temperature sensor circuit with programmable temperature range is proposed for biomedical applications. The proposed circuit consists of temperature sensor core circuit and programmable temperature range digital interface circuit. Both circuits are able to be operated at 1.0 V. The proposed temperature sensor circuit is operated in weak inversion region of MOSFETs. The proposed digital interface circuit converts current into time using Current-to-Time Converter (ITC) and converts time to digital data using counter. Temperature range can be programmed by adjusting pulse width of the trigger and clock frequency of counter. The proposed circuit was simulated using HSPICE with 1P, 5M, 3-wells, 0.18-μm CMOS process (BSIM3v3.2, LEVEL53). From the simulation of proposed circuit, temperature range is programmed to be 0 °C to 100 °C, it is obtained that resolution of the proposed circuit is 0.392 °C with -0.89/+0.29 °C inaccuracy and the total power consumption is 22.3 μW in 25 °C.

Low Common-Mode Gain Instrumentation Amplifier Architecture Insensitive to Resistor Mismatches

In this paper, an instrumentation amplifier architecture for biological signal is proposed. First stage of conventional IA architecture was modified by using fully balanced differential difference amplifier and evaluated by using 1P 2M 0.6μm CMOS process. From HSPICE simulation result, lower common-mode voltage can be achieved by proposed IA architecture. Actual fabrication was done and six chips were evaluated. From the evaluation result, average common-mode gain of proposed IA architecture is 10.84 dB lower than that of conventional one without requiring well-matched resistors. Therefore, the proposed IA architecture is suitable for biological signal processing

A New Instrumentation Amplifier Architecture Based on Differential Difference Amplifier for Biological Signal Processing

In this paper, a new Instrumentation Amplifier (IA) architecture for biological signal pro-cessing is proposed. First stage of the proposed IA architecture consists of fully balance differential difference amplifier and three resistors. Its second stage was designed by using differential difference amplifier and two resistors. The second stage has smaller number of resistors than that of conventional one. The IA architectures are simulated and compared by using 1P 2M 0:6-m CMOS process. From HSPICE simulation result, lower common-mode voltage can be achieved by the proposed IA architecture. Average common-mode gain (Ac) of the proposed IA architecture is 31:26 dB lower than that of conventional one under 3% resistor mismatches condition. Therefore, the Ac of the proposed IA architecture is more insensitive to resistor mismatches and suitable for biological signal processing

ヒト腸内酪酸産生菌Faecalibacterium属細菌の新規分類マーカーの確立と定量法の開発

東京農業大学博士(農学)2022doctoral thesi

Validation of MALDI-TOF MS devices in reanalysis of unidentified pathogenic bacteria detected in blood cultures

In hospital microbial laboratories, morphological and biochemical analyses are performed to identify pathogenic microbes;however, these procedures lack rapidity and accuracy. Recently, Matrix-Assisted Laser Desorption/Ionization Time-of-Flight Mass Spectrometry (MALDI-TOF MS) has been clinically utilized, and is expected to enable rapid and accurate microbial identification. We aimed to validate two MALDI-TOF MS devices available in Japan: the VITEK-MS (BioMérieux) and the Microflex LT (Bruker Daltonics). Clinically isolated bacteria, 100 samples in all, detected in blood cultures but incompletely identified by conventional procedures, were reanalyzed using the two devices. The VITEK-MS and Microflex LT, respectively, identified 49% (49/100) and 80% (80/100) of the tested bacteria at the species level, as well as 96% (96/100) and 95% (95/100) at the genus level. Among those reidentified strains, 26% (26/100) at the species level and 88% (88/100) at the genus level were concordant with each other, though three strains were unmatched. Moreover, four bacterial strains were unable to be identified using the VITEK-MS, versus five using the Microflex LT. MALDI-TOF MS devices can provide more rapid and accurate bacterial identification than ever before;however, the characteristics of each system were slightly different;therefore, it is necessary to understand the difference in performance of MALDI-TOF MS models