BODY BIAS CONTROL FOR A COARSE GRAINED RECONFIGURABLE ACCELERATOR IMPLEMENTED WITH SILICON ON THIN BOX TECHNOLOGY

ABSTRACT For low power yet high performance processing in battery driven devices, a coarse grained reconfigurable accelerator called Cool Mega Array (CMA)-SOTB is implemented by using Silicon on Thin BOX (SOTB), a new process technology developed by the Low-power Electronics Association & Project (LEAP). A real chip using a 65nm experimental process achieved a sustained performance of 192MOPS with a power supply of 0.4V and power consumption of 1.7mW. A clock frequency of 89MHz was achieved with a power supply of just 0.4V when a forward bias voltage was given. When using a reverse bias, the leakage current could be suppressed to less than 20µW in the stand-by mode. The key concept of CMA-SOTB is maintaining a balance between performance and leakage current by independently controlling the bias voltages of the PE array and the microcontroller. Evaluations of the operational frequency and power consumption of filter application programs shed light on how to find the combination of bias voltages that achieves the best energy efficiency for a required performance. The range of advantageous power supply voltage for a required performance considering the body bias was also found

VLANbased Minimal Paths in PC Cluster with Ethernet on Mesh and Torus

Abstract In a PC cluster with Ethernet, well-distribute

An FPGA-Based, Multi-model Simulation Method for Biochemical Systems

Modeling and simulation of a cellular system on computers are now becoming an essential process in biological researches. However, modern PCs can\u27t provide enough performance to simulate large-scale biochemical networks. ReCSiP is the alternative FPGA-based solution for biochemical simulations. In this paper, the novel method of biochemical simulation with multiple reaction models on an FPGA is proposed. The method generates optimal circuit and its optimal schedule for each simulation models written in SBML, the standard markup language in systems biology. ReCSiP has a Xilinx\u27s XC2VP70 and achieved over 20-fold speedup compared to Intel’s PentiumIII 1.13GHz.19th IEEE International Parallel and Distributed Processing Symposium (IPDPS\u2705), April 4-8, 2005, Denver, Colorad

Pipeline scheduling with input port constraints for an FPGA-based biochemical simulator

This paper discusses design methodology of high-throughput arithmetic pipeline modules for an FPGA-based biochemical simulator. Since limitation of data-input bandwidth caused by port constraints often has a negative impact on pipeline scheduling results, we propose a priority assignment method of input data which enables efficient arithmetic pipeline scheduling under given input port constraints. Evaluation results with frequently used rate-law functions in biochemical models revealed that the proposed method achieved shorter latency compared to ASAP and ALAP scheduling with random input orders, reducing hardware costs by 17.57% and by 27.43% on average, respectively.The original publication is available at www.springerlink.co

TCI Tester: A Chip Tester for Inductive Coupling Wireless Through-Chip Interface

The building block computation system is constructed by stacking various chips three-dimensionally. The stacked chips incorporate the same TCI IP (Through Chip Interface Intellectual Property) but cannot provide identical characteristics, requiring adjustments in power supply and bias voltage. However, providing characteristics measurement hardware for all chips is difficult due to the limitation of chip area or pin numbers. To address this problem, we developed TCI Tester, a small chip to measure electric characteristics by stacking on TCI of every chip. By stacking two TCI Tester chips, it appears that the up-directional data transfer has a stricter condition than down directional one on power supply voltage and operational frequency. Also, the transfer performance is poorer than designed. Similar measurement results are obtained by stacking TCI Tester on other chips with TCI IP. To investigate the reason, we analyzed the power grid resistance of various chips with the TCI IP. Results also showed that the chips with higher resistance have a narrow operational condition and poorer performance. The results suggest that the power grid design is important for keeping the performance through the TCI channel