Effective System Level Simulation Techniques and Cross-Layer Perspectives on Low Power Design

International audienc

Organic Computing at the System on Chip Level

Abstract—The evolution of CMOS technologies leads to integrated circuits with ever smaller device sizes, lower supply voltage, higher clock frequency and more process variability. Intermittent faults effecting logic and timing are becoming a major challenge for future integrated circuit designs. This paper presents an Organic Computing inspired SoC architecture which applies self-organization and self-calibration concepts to build reliable SoCs with lower overheads and a broader fault coverage than classical fault-tolerance techniques. We demonstrate the feasibility of this approach by example on the processing pipeline of a public-domain RISC CPU core. I

Buffer schemes for runtime reconfiguration of function variants in communication systems

This contribution is an extension of our work, which introduced distributed buffer schemes for runtime reconfiguration in adaptive processing architectures, e.g., for streaming media applications. We propose a reconfiguration control protocol and depict results for a reference system implementation. With dynamic reconfiguration, area-cost of field-programmable logic (FPL) can be reduced by reuse, and potential for adaptive signal processing techniques can be enabled. The challenge with runtime reconfiguration is the reconfiguration latency. Given the limitation regarding reconfiguration latency with traditional approaches, we proposed distributed buffer schemes. The simulation results show that our approach enables potential for runtime reconfiguration for adaptive signal processing under real-time constraints. The proposed control protocol enables regular structures for modular based dynamic reconfiguration handling. Finally, we present implementation details and results of an architectural system implementation

Fast scenario-based design space exploration using feature selection

This paper presents a novel approach to efficiently perform early system level design space exploration (DSE) of MultiProcessor System-on-Chip (MPSoC) based embedded systems. By modeling dynamic multi-application workloads using application scenarios, optimal designs can be quickly identified using a combination of a scenario-based DSE and a feature selection algorithm. The feature selection algorithm identifies a representative subset of scenarios, which is used to predict the fitness of the MPSoC design instances in the genetic algorithm of the scenario-based DSE. Results show that our scenario-based DSE provides a tradeoff between the speed and accuracy of the early DSE

Connecting Different Worlds - Technology Abstraction for Reliability-Aware Design and Test

PACS 85.40International audienceThe rapid shrinking of device geometries in the nanometer regime requires new technology-aware design methodologies. These must be able to evaluate the resilience of the circuit throughout all System on Chip (SoC) abstraction levels. To successfully guide design decisions at the system level, reliability models, which abstract technology information, are required to identify those parts of the system where additional protection in the form of hardware or software countermeasures is most effective. Interfaces such as the presented Resilience Articulation Point (RAP) or the Reliability Interchange Information Format (RIIF) are required to enable EDA-assisted analysis and propagation of reliability information. The models are discussed from different perspectives, such as design and test