Analysis of the subthreshold current of pocket or halo-implanted nMOSFETs

In this work, we analyzed the subthreshold current (I/sub D/) of pocket implanted MOSFETs using extensive device simulations and experimental data. We present an analytical model for the subthreshold current applicable for any type of FET and show that the subthreshold current of nMOSFETs, which is mainly due to diffusion, is determined by the internal two-dimensional hole distribution across the device. This hole distribution is affected by the electric potential of the gate and the doping concentration in the channel. The results obtained allow accurate modelling of the subthreshold current of future generation MOS devices

Electric field and interface charge extraction in field-plate assisted RESURF devices

A methodology for extracting the lateral electric field (Ex) in the drain extension of thin silicon-on-insulator high-voltage field-plate assisted reduced surface field (RESURF) devices is detailed including its limits and its accuracy. Analytical calculations and technology computer-aided design device modeling corresponding to experimental data are used. It is shown how to obtain trapped interface charge distributions (e.g., due to hot-carrier injection) from the extracted fields. Thus, a new method for determining the position and quantity of injected charges in the drain extension of RESURF power transistors is introduced

Ideal RESURF Geometries

In order to maximize the OFF-state breakdown voltage (BV) of semiconductor devices, the slope of the electric field in the drift extension along the current flow direction ( $E_{x}$ field) should be zero. This is achieved using the reduced surface field (RESURF) effect. This paper demonstrates a method to construct devices that obey Poisson’s equation and satisfy the ideal RESURF condition giving zero slope in $E_{x}$ throughout the 2-D device region. The designs are obtained by shaping the device geometry and the boundaries and by applying the proper potentials at the boundaries. Using this method, ideal designs of the drift extension have been derived for devices based on graded doping, graded thickness, and graded field-plate potential. In addition, 2-D solutions have been derived for periodic superjunction device geometries. A solution for devices that combine several types of field shaping is demonstrated. Finally, the effect of nonideal geometries on the BV in more realistic geometries is discussed

An improved analytical model for carrier multiplication near breakdown in diodes

The charge carrier contributions to impact ionization and avalanche multiplication are analyzed in detail. A closed-form analytical model is derived for the ionization current before the onset of breakdown induced by both injection current components. This model shows that the ratio of both injection current components affects the multiplication factor at relatively low fields before breakdown, but does not affect the reverse breakdown voltage. Furthermore, the model indicates that in case the ionization coefficients of electrons and holes are quite different in value, which depends upon the semiconductor material, the ionization coefficient of the charge carrier with the highest value can be extracted at those low fields. The one with the lowest value can be obtained by fitting the current close to breakdown. The model is compared and verified with TCAD simulations, and to some extent with experimental data, for silicon p-i-n diodes

A record high 150 GHz f\u3csub\u3emax\u3c/sub\u3e realized at 0.18 μm gate length in an industrial RF-CMOS technology

\u3cp\u3eWe demonstrate that by careful layout optimisation, particularly aimed at reducing the effective gate resistance, a record high maximum oscillation frequency f\u3csub\u3emax\u3c/sub\u3e of 150 GHz can be obtained for an industrial 0.18 μm CMOS process showing a cut-off frequency f\u3csub\u3eT\u3c/sub\u3e of 70 GHz. A very low minimum noise figure and good suppression of the substrate noise using a guard-ring is also shown.\u3c/p\u3

Influence of preamorphizatlon and recrystallization on indium doping profiles in silicon

\u3cp\u3eThe influence of preamorphization and solid-phase epitaxial regrowth on indium doping profile was discussed. Premorphised silicon significantly reduces channeling during indium ion implantation, producing a much more abrupt doping profile. It is suggested that during recrystallization by thermal annealing, indium segregates in front of the moving amorphous/crystalline interface, creating a clearly visible peak in the doping profile. It was also suggested that the indium segregation phenomenon get enhanced at lower temperatures.\u3c/p\u3