2,734 research outputs found

    Five reasons why new Indian Prime Minister Narendra Modi could successfully rekindle US-India relations

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    At the end of September, Indian Prime Minister Narendra Modi is due to make his first state visit to the United States. Hemal Shah argues that despite Modi’s 2005 visa ban and India’s rocky relationship with the US to date, it is possible to be cautiously optimistic about the future relations between the two democratic giants

    “Developing countries should build capacity to have public debates” – Raghuram Rajan

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    Hemal Shah reports from Delhi on a workshop exploring whether there is an emerging democratic growth model in India, Brazil and South Africa, as an alternative to a Chinese-style growth model

    Five reasons why Modi could successfully rekindle US-India relations

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    At the end of September Modi is due to make his first state visit to America. Hemal Shah argues that despite Modi’s 2005 visa ban and India’s rocky relationship with the US to date, it is possible to be cautiously optimistic about the future relations between the two democratic giants

    South Africa’s politics of unemployment

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    LSE alumna Hemal Shah says that South Africans could use their democratic and demographic advantages to tackle their massive unemployment problem

    Falling short: how bad economic choices threaten the US-India relationship and India’s rise

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    A study by authors at the American Enterprise Institute explains how a US-India strategic partnership built on weak economic foundations will likely flounder

    Low Power Processor Architectures and Contemporary Techniques for Power Optimization – A Review

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    The technological evolution has increased the number of transistors for a given die area significantly and increased the switching speed from few MHz to GHz range. Such inversely proportional decline in size and boost in performance consequently demands shrinking of supply voltage and effective power dissipation in chips with millions of transistors. This has triggered substantial amount of research in power reduction techniques into almost every aspect of the chip and particularly the processor cores contained in the chip. This paper presents an overview of techniques for achieving the power efficiency mainly at the processor core level but also visits related domains such as buses and memories. There are various processor parameters and features such as supply voltage, clock frequency, cache and pipelining which can be optimized to reduce the power consumption of the processor. This paper discusses various ways in which these parameters can be optimized. Also, emerging power efficient processor architectures are overviewed and research activities are discussed which should help reader identify how these factors in a processor contribute to power consumption. Some of these concepts have been already established whereas others are still active research areas. © 2009 ACADEMY PUBLISHER
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