A low-cost DAC BIST structure using a resistor loop

<div><p>This paper proposes a new DAC BIST (digital-to-analog converter built-in self-test) structure using a resistor loop known as a DDEM ADC (deterministic dynamic element matching analog-to-digital converter). Methods for both switch reduction and switch effect reduction are proposed for solving problems related to area overhead and accuracy of the conventional DAC BIST. The proposed BIST modifies the length of each resistor in the resistor loop via a merging operation and reduces the number of switches and resistors. In addition, the effect of switches is mitigated using the proposed switch effect reduction method. The accuracy of the proposed BIST is demonstrated by the reduction in the switch effect. The experimental results show that the proposed BIST reduces resource usages and the mismatch error caused by the switches.</p></div

Spice simulation result in 7-bit DDEM ADC with <i>P</i> = 64.

<p>Spice simulation result in 7-bit DDEM ADC with <i>P</i> = 64.</p

Pseudocode of the switch effect reduction method.

<p>Pseudocode of the switch effect reduction method.</p

Hardware overhead comparison with previous works (<i>μm</i>²).

<p>Hardware overhead comparison with previous works (<i>μm</i>²).</p

A mismatch error comparison graph.

<p>A mismatch error comparison graph.</p

Resistor string change with different connections.

<p>Resistor string change with different connections.</p

Error voltage comparison with previous works (LSB).

<p>Error voltage comparison with previous works (LSB).</p

An example of a resistor string form.

<p>An example of a resistor string form.</p

Histogram-Based Calibration Method for Pipeline ADCs

<div><p>Measurement and calibration of an analog-to-digital converter (ADC) using a histogram-based method requires a large volume of data and a long test duration, especially for a high resolution ADC. A fast and accurate calibration method for pipelined ADCs is proposed in this research. The proposed calibration method composes histograms through the outputs of each stage and calculates error sources. The digitized outputs of a stage are influenced directly by the operation of the prior stage, so the results of the histogram provide the information of errors in the prior stage. The composed histograms reduce the required samples and thus calibration time being implemented by simple modules. For 14-bit resolution pipelined ADC, the measured maximum integral non-linearity (INL) is improved from 6.78 to 0.52 LSB, and the spurious-free dynamic range (SFDR) and signal-to-noise-and-distortion ratio (SNDR) are improved from 67.0 to 106.2dB and from 65.6 to 84.8dB, respectively.</p></div