Blood-testis barrier integrity depends on Pin1 expression in Sertoli cells

The conformation and function of a subset of serine and threonine-phosphorylated proteins are regulated by the prolyl isomerase Pin1 through isomerization of phosphorylated Ser/Thr-Pro bonds. Pin1 is intensely expressed in Sertoli cells, but its function in this post mitotic cell remains unclear. Our aim was to investigate the role of Pin1 in the Sertoli cells. Lack of Pin1 caused disruption of the blood-testis barrier. We next investigated if the activin pathways in the Sertoli cells were affected by lack of Pin1 through immunostaining for Smad3 protein in testis tissue. Indeed, lack of Pin1 caused reduced Smad3 expression in the testis tissue, as well as a reduction in the level of N-Cadherin, a known target of Smad3. Pin1−/− testes express Sertoli cell marker mRNAs in a pattern similar to that seen in Smad3+/− mice, except for an increase in Wt1 expression. The resulting dysregulation of N-Cadherin, connexin 43, and Wt1 targets caused by lack of Pin1 might affect the mesenchymal–epithelial balance in the Sertoli cells and perturb the blood-testis barrier. The effect of Pin1 dosage in Sertoli cells might be useful in the study of toxicant-mediated infertility, gonadal cancer, and for designing male contraceptives

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Department of Electrical Engineeringclos

A PVT-Robust Low Reference Spur Injection-Locked Clock Multiplier Using a Voltage-Domain Period-Calibrating Loop

This paper presents a low-reference-spur and low-jitter injection-locked clock multiplier (ILCM). To secure these performances over PVT-variations, we propose the use of a voltage-domain period-calibrating loop (VDPCL) in the ILCM that monitors the intrinsic period of the VCO and stores this information as the charges in a capacitor. By evaluating the voltage of the capacitor, it is possible to correct the free-running frequency of the VCO. By iteratively accumulating charges, the precision of the calibration can be increased. The measured reference spur and RMS jitter were -59 dBc and 450 fs, respectively, and their degradations over the PVT were less than 1.5 dB and 50 fs, respectively

An ultra-low phase noise all-digital multi-frequency generator using injection-locked DCOs and time-interleaved calibration

This work presents an ultra-low phase noise and all-digital frequency generator, providing multiple output-frequencies. In a time-interleaved fashion, the proposed calibrator can continue to correct the multiple output-frequencies of injection-locked DCOs, which can change independently between 0.9 and 1.2GHz. Due to the time-interleaved calibrator, operating continuously in the background, each injection-locked DCO can maintain the excellent noise performance; the 1-MHz phase noise and the RMS-jitter at 930MHz were -132.2dBc/Hz and 310fs, and its variation across temperatures and voltages was less than 9%. ?? 2017 IEEE

A Low-Jitter Injection-Locked Multi-Frequency Generator Using Digitally Controlled Oscillators and Time-Interleaved Calibration

This paper presents a low-jitter, injection-locked frequency generator that can provide multiple output frequencies concurrently. The injection-locked digitally controlled oscillators (DCOs) can be controlled separately so that their output frequencies can be changed independently between 0.9 and 1.2 GHz in 15-MHz steps. Due to the proposed time-interleaved frequency calibrator that operates continuously in the background, all injection-locked DCOs are ensured to maintain excellent jitter performance against process, voltage, and temperature (PVT) variations. As a prototype, the proposed injection-locked, multi-frequency generator (ILMFG) was designed to generate two independently controlled output signals, and it was fabricated in a 65-nm CMOS technology. The 1-MHz phase noise and the rms jitter integrated from 1 kHz to 40 MHz of the 960-MHz output signal were -133.5 dBc/Hz and 375 fs, respectively. The degradation of rms jitter was restricted to less than 10%. The silicon area was 0.05 mm(2), and the total power consumption was 7.7 mW when generating two different output frequencies

A wideband dual-mode LC-VCO with a switchable gate-biased active core

A wideband inductance-capacitance voltage-controlled oscillator (VCO) with a gm-switching technique was designed and fabricated in the 65-nm CMOS process. With a switchable secondary gate-biased active core and a primary core, the VCO operates in two different modes. In the LF mode, in which switches turn on the secondary core, the increased start-up gain facilitates LF oscillation. In the HF mode, in which the switches isolate the secondary core from the primary core, the reduced capacitive loading allows for HF oscillation. In addition, since the gate bias of the secondary core transistors guarantees the high transconductance of the secondary core, the switch size can be minimized, which further extends the upper boundary of the oscillation frequency. The VCO achieved a 41\% frequency range, i.e., 3.36-5.1 GHz, and a phase noise of-123.1 dBc/Hz at an offset of 1 MHz from an output frequency of 4.21 GHz. The active silicon area was 0.24 mm2, and the power consumption was 8.7 mW at 5 GHz.close1

A Low-Integrated-Phase-Noise 27-30-GHz Injection-Locked Frequency Multiplier With an Ultra-Low-Power Frequency-Tracking Loop for mm-Wave-Band 5G Transceivers

An ultra-low-phase-noise injection-locked frequency multiplier (ILFM) for millimeter wave (mm-wave) fifth-generation transceivers is presented. Using an ultra-low-power frequency-tracking loop (FTL), the proposed ILFM is able to correct the frequency drifts of the quadrature voltage-controlled oscillator of the ILFM in a real-time fashion. Since the FTL is monitoring the averages of phase deviations rather than detecting or sampling the instantaneous values, it requires only 600 mu W to continue to calibrate the ILFM that generates an mm-wave signal with an output frequency from 27 to 30 GHz. The proposed ILFM was fabricated in a 65-nm CMOS process. The 10-MHz phase noise of the 29.25-GHz output signal was -129.7 dBc/Hz, and its variations across temperatures and supply voltages were less than 2 dB. The integrated phase noise from 1 kHz to 100 MHz and the rms jitter were -39.1 dBc and 86 fs, respectively

Injection-locked frequency multiplier with a continuous frequency-tracking loop for 5G transceivers

This work presents a low-phase noise (PN) mm-wave injection-locked frequency multiplier (ILFM) using an ultra-low power frequency-tracking loop (FTL). Monitoring the averages of phase deviations rather than detecting the instantaneous values, the FTL consumed only 600W to calibrate the mm-wave ILFM generating a frequency between 27 and 30GHz. While consuming low power, the proposed FTL effectively regulated the PN degradation, which was less than 2dB up to 100MHz offset across VT variations

A PVT-Robust -39dBc 1kHz-to-100MHz Integrated-Phase-Noise 29GHz Injection-Locked Frequency Multiplier with a 600??W Frequency-Tracking Loop Using the Averages of Phase Deviations for mm-Band 5G Transceivers

To meet requirements of high data-rates, RF transceivers for a 5G standard must have an ultra-wide bandwidth in a mm-wave band. A big challenge of a 5G transceiver is to generate ultra-low-PN (phase noise) local-oscillator (LO) signals to suppress integrated PN (IPN) over such an extremely wide bandwidth. A PLL that directly generates mm-band LO signals is not a good choice due to power-hungry frequency dividers and relatively poor PN. An mm-band LO generator, cascading a GHz-range PLL and a frequency multiplier as shown in Fig. 19.2.1, is an attractive solution. First, a GHz-range PLL can have a higher FOM than a mm-band PLL [1]. Second, the cascaded architecture is naturally able to support the bands for 2G to 4G standards. An injection-locked frequency multiplier (ILFM) is popular in a mm-band, achieving ultra-low PN even in a tight power budget. However, the vulnerability of PN to PVT variations is a critical problem. For an ILFM, the PN performance can be improved only when the free-running VCO frequency, fVCO, and the target frequency are sufficiently close within the lock range, fL, which is very narrow, especially, at high frequencies. To calibrate fVCO over PVT, many frequency-tracking loops (FTLs) have used a power-hungry circuit (such as a replica-VCO, a TDC, and a counter) operating at fVCO, but they were not suitable for a mm-band ILFM. The sub-sampling FTL [2] used the voltage levels of the VCO outputs, momentarily sampled by injection pulses. However, for the accurate sampling, the pulse width of the injection pulses must be very narrow, since the sampling occurs at the edges of the pulses. For a mm-band VCO, the pulse width must be less than 10ps, but these narrow pulses limit the injection strength and fL. In the mm-band ILFM of [3], the mixers and dividers consumed a lot of power. An envelope detector was used for another mm-band ILFM to enable the calibration operating at low frequencies [4], but it cannot detect fVCO after the VCO is injection-locked and prevent PN degradation due to real-time drifts of fVCO