25 research outputs found

    Coordinated tethering for devices with multi-RAT capabilities: An algorithmic solution and performance analysis

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    One challenging requirement of the Internet of Things (IoTs) is related to the capability of the wireless access network to be able to provide internet connectivity to a very large number of devices, compared to conventional cellular use cases. With the WiFi technology being the spearhead of the wireless local area networks (WLANs), the exploitation of already deployed WLANs has gained ground as a practical and efficient approach towards increasing the spectral efficiency of wireless networks. Based on the coordinated tethering concept, we introduce a purely wireless heterogeneous network deployment, where cellular and WLAN radio resources are optimally coordinated towards the universal maximization of the user's throughput. The wireless users (smartphones, IoT devices, etc.) are coordinated by the evolved node B (eNB) about their role in the network (access point (AP) or normal user) and the access technology they have to employ. The performance of the new approach has been investigated based on a theoretical framework that has been developed. In this context, closed-form expressions are derived for important statistical characteristics of the system's output signal-to-interference plus noise ratio (SINR) for the single-user case with multiple interferers. Then, this approach is extended to a multi-user multi-cellular system and a greedy algorithm is proposed for optimizing the system performance. Various numerical and simulation results have presented, which show that the proposed multi-cellular multi-radio access technology (RAT) scheme with coordinated tethering may increase spectral efficiency. © 2019 Elsevier B.V

    Wideband Propagation Measurements and Modeling in Indoor Environment

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    This paper presents the results of wideband measurements of an indoor wireless radio channel at 1.8 GHz. Propagation measurements were carried out in an indoor environment at the Technical University of Athens with a network analyzer. From the measured impulse response (IR) profiles collected, mean excess delay τm and root mean square of delay spread τrms have been estimated. Statistical analysis of delay spread and amplitude fading has been performed. Comparison with simulation results extracted from SIRCIM Simulator package has also been made

    On Directly Modulated Reflective Semiconductor Optical Amplifier with Assistance of Birefringent Fiber Loop

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    Reflective Semiconductor Optical Amplifiers (RSOAs) are essential devices for the development of new generation networks that rely on the convergence of optical and RF communications. Despite their proven potential for direct modulation, RSOAs’ electro-optic response is limited by their finite bandwidth, which hinders their employment both for signal amplification and modulation at the data rates envisioned by the target applications. In this paper, we elaborate on exploiting a Birefringent Fiber Loop (BFL) to enhance the operation of RSOAs as intensity modulators. We apply a mathematically and computationally reduced model to simulate the RSOA response in the time domain, and correlate it with that of the BFL in the frequency domain. We validate the model’s predictions by an extensive comparison of the simulation against experimental results. The reasonable theoretical findings allow us to establish the employed model as an efficient tool for describing electrically driven RSOA operation and its improvement by means of optical notch filtering. Furthermore, we evaluate and quantify the performance of the scheme and the potential range of RSOA direct modulation capability extension enabled by the BFL, which complies with the experimentally observed trends. The outcomes of this thorough study highlight the BFL supportive role in rendering feasible RSOAs’ direct modulation at data rates beyond those deemed possible by their nominal modulation bandwidth. © 2022 by the authors. Licensee MDPI, Basel, Switzerland

    30 Gb/s all-optical clock recovery circuit

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