Hyperadiponectinemia enhances bone formation in mice

<p>Abstract</p> <p>Background</p> <p>There is growing evidence that adiponectin, a physiologically active polypeptide secreted by adipocytes, controls not only adipose tissue but also bone metabolism. However, a role for adiponectin in bone development remains controversial.</p> <p>Methods</p> <p>We therefore investigated the endocrine effects of adiponectin on bone metabolism using 12-week-old male transgenic (Ad-Tg) mice with significant hyperadiponectinemia overexpressing human full-length adiponectin in the liver.</p> <p>Results</p> <p>In Ad-Tg mice, the serum level of osteocalcin was significantly increased, but the levels of RANKL, osteoprotegerin, and TRAP5b were not. Bone mass was significantly greater in Ad-Tg mice with increased bone formation. In contrast, bone resorption parameters including the number of osteoclasts and eroded surface area did not differ between Ad-Tg and their littermates.</p> <p>Conclusions</p> <p>These findings demonstrate that hyperadiponectinemia enhances bone formation in mice.</p

REDEFIS : A System with a Redefinable Instruction Set Processor

The 19th Annual Symposium on Integrated Circuits and Systems Design : Brazil : August 28 - September 1, 2006The growing complexity and production cost of processor-based systems have imposed big constraints in SoC design of new systems. GPPs and ASICs are unable to fit the tight performance or power constraints, or too complex to design in short TAT/TTM. REDEFIS is a HW/SW design platform for high level, efficient implementation of ASIPs/engines for SoC systems. It is composed of a reconfigurable instruction-set processor, capable to redefine its ISA according to the user application written in high level C language, and a set of design tools (an ISA Generator and a retargetable compiler). These processors can be used as flexible engines in embedded MPSoC systems, where its ISA is fully customized and design is done at high level C (no HDL writing is necessary). In this paper we present the Redefis design platform and an implementation of our dynamically reconfigurable ISA processor (codename Vulcan). Our results demonstrate the effectiveness of the system for encryption and bitwise applications

REDEFIS : A System with a Redefinable Instruction Set Processor

The growing complexity and production cost of processor-based systems have imposed big constraints in SoC design of new systems. GPPs and ASICs are unable to fit the tight performance or power constraints, or too complex to design in short TAT/TTM. REDEFIS is a HW/SW design platform for high level, efficient implementation of ASIPs/engines for SoC systems. It is composed of a reconfigurable instruction-set processor, capable to redefine its ISA according to the user application written in high level C language, and a set of design tools (an ISA Generator and a retargetable compiler). These processors can be used as flexible engines in embedded MPSoC systems, where its ISA is fully customized and design is done at high level C (no HDL writing is necessary). In this paper we present the Redefis design platform and an implementation of our dynamically reconfigurable ISA processor (codename Vulcan). Our results demonstrate the effectiveness of the system for encryption and bitwise applications.The 19th Annual Symposium on Integrated Circuits and Systems Design : Brazil : August 28 - September 1, 200