The Japanese Labor Market in a Comparative Perspective with the United States: A Transaction-Cost Interpretation

This study offers a comparative analysis of a number of Japanese labor market features in relation to the U.S. The author examines employer-employee attachment, workforce adjustment, and industrial relations including unique Japanese institutions such as joint consultation and consensus-based decision making. Hashimoto argues that cultural-traditional influences, which shape the transaction-cost environment, interacted with technological progress in shaping the various uniquely-Japanese labor market features.https://research.upjohn.org/up_press/1101/thumbnail.jp

Evaluating Methods for Evaluating Instruction: The Case of Higher Education

This paper develops an original measure of learning in higher education, based on grades in subsequent courses. Using this measure of learning, this paper shows that student evaluations are positively related to current grades but unrelated to learning once current grades are controlled. It offers evidence that the weak relationship between learning and student evaluations arises, in part, because students are unaware of how much they have learned in a course. The paper concludes with a discussion of easily-implemented, optimal methods for evaluating teaching.

B²N²: Resource efficient Bayesian neural network accelerator using Bernoulli sampler on FPGA

A resource efficient hardware accelerator for Bayesian neural network (BNN) named B²N², Bernoulli random number based Bayesian neural network accelerator, is proposed. As neural networks expand their application into risk sensitive domains where mispredictions may cause serious social and economic losses, evaluating the NN’s confidence on its prediction has emerged as a critical concern. Among many uncertainty evaluation methods, BNN provides a theoretically grounded way to evaluate the uncertainty of NN’s output by treating network parameters as random variables. By exploiting the central limit theorem, we propose to replace costly Gaussian random number generators (RNG) with Bernoulli RNG which can be efficiently implemented on hardware since the possible outcome from Bernoulli distribution is binary. We demonstrate that B²N² implemented on Xilinx ZCU104 FPGA board consumes only 465 DSPs and 81661 LUTs which corresponds to 50.9% and 14.3% reductions compared to Gaussian-BNN (Hirayama et al., 2020) implemented on the same FPGA board for fair comparison. We further compare B²N² with VIBNN (Cai et al., 2018), which shows that B²N² successfully reduced DSPs and LUTs usages by 50.9% and 57.9%, respectively. Owing to the reduced hardware resources, B²N² improved energy efficiency by 7.50% and 57.5% compared to Gaussian-BNN (Hirayama et al., 2020) and VIBNN (Cai et al., 2018), respectively

Avoiding Soft Error-Induced Illegal Memory Accesses in GPU with Inter-Thread Communication

2023 IEEE 29th International Symposium on On-Line Testing and Robust System Design (IOLTS), 3-5 July 2023, Crete, GreeceA soft error caused by terrestrial neutrons poses a threat to the reliability of safety-critical systems, such as self-driving applications. These applications, often comprised of neural networks, rely on graphic processing units (GPUs) due to their requirement for massive parallel computation. While neural networks inherently include redundant computation and possess a certain level of error tolerance, detectable unrecoverable errors (DUEs) can be more detrimental than silent data corruption (SDC), as they can result in temporary service unavailability. This study specifically focuses on addressing illegal memory access, a primary cause of DUEs, and proposes a programming method that can detect illegal addresses. In the single instruction, multiple threads (SIMT) scheme, the data address is regularly calculated based on the thread ID, and this regularity is exploited to identify illegal addresses through inter-thread communication. To evaluate the effectiveness of the proposed method, fault injection campaigns were conducted for matrix multiplication, vector addition, and transposition. The experimental results indicate that the proposed method resulted in a reduction of the DUE rate by 17.3%, 86.8%, and 87.1% for these respective operations