Deterministic dynamic element matching: an enabling technology for SoC built-in-self-test

The analog-to-digital converter (ADC) is a key building block of today\u27s high-volume systems-on-a-chip (SoCs). Built-in-self-test (BIST) is the most promising solution to testing deeply-embedded ADCs. Cost-effective stimulus source with on-chip integrability has been viewed as the bottleneck of ADC BIST, and consequentially the bottleneck of SoC BIST and BIST-based self-calibration. The deterministic dynamic element matching (DDEM) technique has been proposed as a solution to this problem;In this work, rigorous theoretical analysis is presented to show the performance of a DDEM digital-to-analog converter (DAC) as an ADC linearity test stimulus source. Guided by the insight obtained this analysis, a systematic approach for cost-effective DDEM DAC design is proposed. Two generations of DDEM DACs have been designed, fabricated, and measured. 12-bit equivalent linearity was achieved from the first DDEM DAC with 8-bit apparent resolution and less than 5-bit raw linearity after systematic error compensation. The achieved 12-bit linearity outperforms any on-chip stimulus source in literature. Based on the first design, a new DDEM DAC with 12-bit apparent resolution, 10-bit raw linearity, and 9-bit DDEM switching was designed with improved design technique. This DAC was fabricated in standard 0.5-pm CMOS technology with a core die area of 2 mm2. Clear ramp signals could be observed on an oscilloscope when the DDEM DAC was clocked at 100 MHz. Laboratory testing results confirmed that the new DDEM DAC achieved at least a 16-bit equivalent linearity; this was limited by the available instrumentation, which has 18-bit linearity. It outperforms any previously reported on-chip stimulus source in terms of ADC BIST performance by 5 bits. The robust performance, low cost, and short design cycle for on-chip implementation make DDEM an enabling technology for SoC BIST and self-calibration;Two new approaches based on DDEM are developed to further boost the die area efficiency, improving the basic DDEM approach. The first is termed segmented DDEM, and the second is dither-incorporated DDEM (DiDDEM). It has been shown through mathematical analysis and simulation that these can maintain the performance of the basic DDEM approach while greatly reducing the implementation cost

An Adaptive Self-Interference Cancelation/Utilization and ICA-Assisted Semi-Blind Full-Duplex Relay System for LLHR IoT

In this article, we propose a semi-blind full-duplex (FD) amplify-and-forward (AF) relay system with adaptive self-interference (SI) processing assisted by independent component analysis (ICA) for low-latency and high-reliability (LLHR) Internet of Things (IoT). The SI at FD relay is not necessarily canceled as much as possible like the conventional approaches, but is canceled or utilized based on a signal-to-residual-SI ratio (SRSIR) threshold at relay. According to the selected SI processing mode at relay, an ICA-based adaptive semi-blind scheme is proposed for signal separation and detection at destination. The proposed FD relay system not only features reduced signal processing cost of SI cancelation but also achieves a much higher degree of freedom in signal detection. The resulting bit error rate (BER) performance is robust against a wide range of SRSIR, much better than that of conventional FD systems, and close to the ideal case with perfect channel state information (CSI) and perfect SI cancelation. The proposed system also requires negligible spectral overhead as only a nonredundant precoding is needed for ambiguity elimination in ICA. In addition, the proposed system enables full resource utilization with consecutive data transmission at all time and same frequency, leading to much higher throughput and energy efficiency than the time-splitting and power-splitting-based self-energy recycling approaches that utilize only partial resources. Furthermore, an intensive analysis is provided, where the SRSIR thresholds for the adaptive SI processing mode selection and the BER expressions with ICA incurred ambiguities are derived

Treating Self-Interference as Source: An ICA Assisted Full-Duplex Relay System

We investigate an amplify-and-forward (AF) full-duplex (FD) relay system, where the FD incurred self-interference (SI), through partial cancelation at relay, is treated as a useful source at destination to enhance degree of freedom in signal detection, while reducing the signal processing cost of SI cancelation. An independent component analysis (ICA) based equalization structure is employed at destination to separate and detect the desired signal from the residual SI in a semi-blind way. The mode of SI cancelation at relay is chosen adaptively based on the threshold of signal-to-interference ratio (SIR) at relay. The proposed FD relay system not only features reduced signal processing cost of SI cancelation, but also achieves much higher energy efficiency (EE) than conventional FD relay systems where SI is canceled as much as possible. Also, the proposed system enables full resource utilization via consecutive data transmission at all time and the same frequency, leading to much higher throughput and EE than the conventional time-splitting and power-splitting based SI recycling approaches that occupy partial resources. Last but not least, the proposed system demonstrates a bit error rate (BER) performance that is robust against a wide range of SI and close to the ideal case with perfect channel state information (CSI) and perfect SI cancelation, while requiring no training sequence for estimation of any channel involved

Toward URLLC: A Full Duplex Relay System with Self-Interference Utilization or Cancellation

Ultra-reliable low-latency communication (URLLC) is one of the key use cases of 5G wireless communications to facilitate specific application scenarios with stringent latency and reliability demands, such as industrial automation and Tactile Internet. A full duplex (FD) relay with simultaneous transmission and reception in the same frequency band is an effective approach to enhance the reliability of cell-edge user terminals by significantly suppressing self-interference (SI). However, the signal processing latency at FD relay due to SI cancellation, referred to as relaying latency, takes a significant part in the end-to-end latency, and therefore should be minimized, while guaranteeing high reliability. In this article, we first present an up-to-date overview of the end-to-end latency for an FD relay system, addressing physical layer challenges. We investigate the possible solutions in the literature to achieve the goal of URLLC. The efficient solution is to allow a simple amplify-and-forward FD relay mode with low-complexity SI radio frequency and analog cancellations, and process the residual SI alongside the desired signal at the base station in an adaptive manner, rather than being cancelled at relay in the digital domain. Also, the residual SI can be utilized at the base station to enhance the reliability and degree of freedom in signal processing, not necessarily being cancelled as much as possible. The FD relay assisted system with adaptive SI utilization or cancellation enables extended network coverage, enhanced reliability, and reduced latency compared to the existing overview work

Deterministic dynamic element matching: an enabling technology for SoC built-in-self-test

The analog-to-digital converter (ADC) is a key building block of today's high-volume systems-on-a-chip (SoCs). Built-in-self-test (BIST) is the most promising solution to testing deeply-embedded ADCs. Cost-effective stimulus source with on-chip integrability has been viewed as the bottleneck of ADC BIST, and consequentially the bottleneck of SoC BIST and BIST-based self-calibration. The deterministic dynamic element matching (DDEM) technique has been proposed as a solution to this problem;In this work, rigorous theoretical analysis is presented to show the performance of a DDEM digital-to-analog converter (DAC) as an ADC linearity test stimulus source. Guided by the insight obtained this analysis, a systematic approach for cost-effective DDEM DAC design is proposed. Two generations of DDEM DACs have been designed, fabricated, and measured. 12-bit equivalent linearity was achieved from the first DDEM DAC with 8-bit apparent resolution and less than 5-bit raw linearity after systematic error compensation. The achieved 12-bit linearity outperforms any on-chip stimulus source in literature. Based on the first design, a new DDEM DAC with 12-bit apparent resolution, 10-bit raw linearity, and 9-bit DDEM switching was designed with improved design technique. This DAC was fabricated in standard 0.5-pm CMOS technology with a core die area of 2 mm2. Clear ramp signals could be observed on an oscilloscope when the DDEM DAC was clocked at 100 MHz. Laboratory testing results confirmed that the new DDEM DAC achieved at least a 16-bit equivalent linearity; this was limited by the available instrumentation, which has 18-bit linearity. It outperforms any previously reported on-chip stimulus source in terms of ADC BIST performance by 5 bits. The robust performance, low cost, and short design cycle for on-chip implementation make DDEM an enabling technology for SoC BIST and self-calibration;Two new approaches based on DDEM are developed to further boost the die area efficiency, improving the basic DDEM approach. The first is termed segmented DDEM, and the second is dither-incorporated DDEM (DiDDEM). It has been shown through mathematical analysis and simulation that these can maintain the performance of the basic DDEM approach while greatly reducing the implementation cost.</p

A 0.0014 mm2 150 nW CMOS Temperature Sensor with Nonlinearity Characterization and Calibration for the −60 to +40 °C Measurement Range

This work presents a complementary metal&ndash;oxide&ndash;semiconductor (CMOS) ultra-low power temperature sensor chip for cold chain applications with temperatures down to &minus;60 &deg;C. The sensor chip is composed of a temperature-to-current converter to generate a current proportional to the absolute temperature (PTAT), a current controlled oscillator to convert the current to a frequency signal, and a counter as the frequency-to-digital converter. Unlike the conventional linear error calibration method, the nonlinear error of the PTAT current under the low temperature range is fully characterized based on the device model files provided by the foundry. Simulation has been performed, which clearly shows the nonlinear model is much more accurate than the linear model. A nonlinear error calibration method, which requires only two-point calibration, is then proposed. The temperature sensor chip has been designed and fabricated in a 0.13 &mu;m CMOS process, with a total active die area of 0.0014 mm2. The sensor only draws a 140 nA current from a 1.1 V supply, with the key transistors working in the deep subthreshold region. Measurement results show that the proposed nonlinear calibration can decrease the measurement error from &minus;0.9 to +1.1 &deg;C for the measurement range of &minus;60 to +40 &deg;C, in comparison with the error of &minus;1.8 to +5.3 &deg;C using the conventional linear error calibration

CMOS IC design for wireless medical and health care

This book provides readers with detailed explanation of the design principles of CMOS integrated circuits for wireless medical and health care, from the perspective of two successfully-commercialized applications. Design techniques for both the circuit block level and the system level are discussed, based on real design examples. CMOS IC design techniques for the entire signal chain of wireless medical and health care systems are covered, including biomedical signal acquisition, wireless transceivers, power management and SoC integration, with emphasis on ultra-low-power IC design techniques. • Discusses CMOS integrated circuit design for wireless medical and health care, based on two successfully-commercialized medical and health care applications; • Describes design techniques for the entire signal chain of wireless medical and health care systems; • Focuses on techniques for short-range wireless communication systems; • Emphasizes ultra-low-power IC design techniques; • Enables readers to turn a high performance SoC into to a complex, wireless medical and health care product

Two‐dimensional materials : from mechanical properties to flexible mechanical sensors

Two‐dimensional (2D) materials have great potential in the fields of flexible electronics and photoelectronic devices due to their unique properties derived by special structures. The study of the mechanical properties of 2D materials plays an important role in next‐generation flexible mechanical electronic device applications. Unfortunately, traditional experiment models and measurement methods are not suitable for 2D materials due to their atomically ultrathin thickness, which limits both the theoretical research and practical value of the 2D materials. In this review, we briefly summarize the characterization of mechanical properties of 2D materials by in situ probe nanoindentation experiments, and discuss the effect of thickness, grain boundary, and interlayer interactions. We introduce the strain‐induced effect on electrical properties and optical properties of 2D materials. Then, we generalize the mechanical sensors based on various 2D materials and their future potential applications in flexible and wearable electronic devices. Finally, we discuss the state of the art for the mechanical properties of 2D materials and their opportunities and challenges in both basic research and practical applications.Ministry of Education (MOE)Published versionFundamental Research Funds for the Central Universities, Grant/Award Numbers: 31020190QD010, 3102019PY004, 3102019JC004; Ministry of Education - Singapore, Grant/Award Numbers: MOE2015-T2-2-043, MOE2017-T2-2-136, Tier 1 RG7/18; National Natural Science Foundation of China, Grant/Award Number: 11904289; Natural Science Foundation of Shaanxi Province, Grant/Award Number: 2019JQ- 613; Start-up funds from Northwestern Polytechnical University, Grant/Award Numbers: 19SH020159, 19SH02012

A 3-D Surface Reconstruction with Shadow Processing for Optical Tactile Sensors

An optical tactile sensor technique with 3-dimension (3-D) surface reconstruction is proposed for robotic fingers. The hardware of the tactile sensor consists of a surface deformation sensing layer, an image sensor and four individually controlled flashing light emitting diodes (LEDs). The image sensor records the deformation images when the robotic finger touches an object. For each object, four deformation images are taken with the LEDs providing different illumination directions. Before the 3-D reconstruction, the look-up tables are built to map the intensity distribution to the image gradient data. The possible image shadow will be detected and amended. Then the 3-D depth distribution of the object surface can be reconstructed from the 2-D gradient obtained using the look-up tables. The architecture of the tactile sensor and the proposed signal processing flow have been presented in details. A prototype tactile sensor has been built. Both the simulation and experimental results have validated the effectiveness of the proposed 3-D surface reconstruction method for the optical tactile sensors. The proposed 3-D surface reconstruction method has the unique feature of image shadow detection and compensation, which differentiates itself from those in the literature