A 1.8-GHz CMOS power amplifier using a dual-primary transformer with improved efficiency in the low power region

A 1.8-GHz CMOS power amplifier for a polar transmitter is implemented with a 0.18-mu m RF CMOS process. The matching components, including the input and output transformers, were integrated. A dual-primary transformer is proposed in order to increase the efficiency in the low power region of the amplifier. The loss induced by the matching network for the low-output power region is minimized using the dual-primary transformer. The amplifier achieved a power-added efficiency of 40.7% at a maximum output power of 31.6 dBm. The dynamic range was 34 dB for a supply voltage that ranged from 0.5 to 3.3 V. The low power efficiency was 32% at the output power of 16 dBm.ope

ESD characteristics of GaAs versus silicon diode

The ESD characteristics of GaAs diode are compared with those of Silicon diode. The ESD diodes are designed and implemented using GaAs HBT technology and 0.25 um CMOS technology. The differences of ESD characteristics between GaAs diode and Silicon diode are investigated, simulated and measured. Because the thermal characteristics of GaAs are different from those of Silicon, the ESD characteristics of GaAs device are different from those of Silicon device

A 2.4 GHz Fully Integrated Linear CMOS Power Amplifier With Discrete Power Control

A fully integrated 2.4 GHz CMOS power amplifier (PA) in a standard 0.18 mu m CMOS process is presented. Using a parallel-combining transformer (PCT) and gate bias adaptation, a discrete power control of the PA is achieved for enhancing the efficiency at power back-off. With a 3.3 V power supply, the PA has a peak drain efficiency of 33% at 31 dBm peak output power. By applying discrete power control, a reduction of 650 mA in current consumption can be achieved over the low output power range while satisfying the EVM requirements of WLAN 802.11g and WiMAX 801.16e signals.ope

Analysis and Design of Fully Integrated High-Power Parallel-Circuit Class-E CMOS Power Amplifiers

A design methodology for watt-level, fully integrated CMOS power amplifiers (PAs) is presented. It is based on the analysis of the operation and power loss mechanism of class-E PAs, which includes the effects of a finite dc-feed inductance and an impedance matching transformer. Using the proposed approach, a class-E PA with a 2 x 1:2 step-up on-chip transformer was implemented in a 0.18-mu m CMOS technology. With a 3.3 V supply, the fully integrated PA achieves an output power of 2 W and a power-added efficiency of 31% at 1.8 GHz.ope

Power-combining transformer techniques for fully-integrated CMOS power amplifiers

Fully integrated CMOS power amplifiers (PAs) with parallel power-combining transformer are presented. For the high power CMOS PA design, two types of transformers, series-combining and parallel-combining, are fully analyzed and compared in detail to show the parasitic resistance and the turn ratio as the limiting factor of power combining. Based on the analysis, two kinds of parallel-combining transformers, a two-primary with a 1:2 turn ratio and a three-primary with a 1:2 turn ratio, are incorporated into the design of fully-integrated CMOS PAs in a standard 0.18-mu m CMOS process. The PA with a two-primary transformer delivers 31.2 dBm of output power with 41% of power-added efficiency (PAE), and the PA with a three-primary transformer achieves 32 dBm of output power with 30% of PAE at 1.8 GHz with a 3.3-V power supply.ope