Using System-on-a-Programmable-Chip Technology to Design Embedded Systems

This paper describes the tools, techniques, and devices used to design embedded products with system–on-a-chip (SoC) type solutions using a large Field Programmable Gate Array (FPGA) with an internal processor core. This new FPGA-based approach is called system-on-a-programmable-chip (SoPC ). The performance tradeoffs present in SoPC systems is compared to more traditional design approaches. Commercial devices, processor cores, and CAD tool flows are described. The issues in SoPC hardware/software design tradeoffs are examined and three example SoPC designs are presented as case studies

An introductory digital design course using a low–cost autonomous robot

This paper describes a new digital design laboratory developed for undergraduate students in this electrical and computer engineering curriculum. A top-down rapid prototyping approach with commercial computer-aided design tools and field-programmable logic devices (FPLDs) is used for laboratory projects. Students begin with traditional transistor–transistor logic-based projects containing a few gates and progress to designing a simple 16-bit computer, using very high-speed integrated circuits hardware description language (VHDL) synthesis tools and an FPLD. To help motivate students, the simple computer design is programmed to control a small autonomous robot with two servo drive motors and several sensors. The laboratory concludes with a team-based design project using the robot

System-on-a-Programmable-Chip Development Platforms in the Classroom

Abstract—This paper describes the authors ’ experiences using a system-on-a-programmable-chip (SOPC) approach to support the development of design projects for upper-level undergraduate students in their electrical and computer engineering curriculum. Commercial field-programmable gate-array (FPGA)-based SOPC development boards with reduced instruction set computer (RISC) processor cores are used to support a wide variety of student design projects. A top-down rapid prototyping approach with commercial FPGA computer-aided design tools, a C compiler targeted for the RISC soft-processor core, and a large FPGA with memory is used and reused to support a wide variety of student projects. Index Terms—Altera, field-programmable gate array (FPGA), microblaze, Nios, processor core, system on a chip (SOC), system on a programmable chip (SOPC), Xilinx. I

Multiple Objective Evolutionary Algorithms for Independent, Computationally Expensive Objective Evaluations Approved by:

This thesis is dedicated to my wife and eight children. Without their support this would not have been possible. iii ACKNOWLEDGEMENTS I would like to acknowledge the following who have made this thesis possible: 1. Dr. Darrell Lamm, my mentor and friend for the past 15 years, spent countless hours over these years listening and directing my research efforts. 2. Dr. Mark Clements, my thesis advisor, had the patience to take on a part-time student for this long road. 3. Georgia Tech Research Institute, my employer, provided funding for the qualifying exam, Ph.D research, development of the PRESTO software, and tuition. Without their support I would have never begun this research. 4. Charles Carstensen, of GTRI, saw the potential of Genetic Algorithm application to flare pattern design against infra-red surface to are missiles. Fortunately, he saw the potential before the shooting started

Using FPGAs to Simulate and Implement Digital Design Systems in the Classroom

Abstract–Field–Programmable Gate Arrays (FPGAs) have gained widespread popularity in digital design laboratories. Their flexibility and relatively low cost make them ideal pedagogical resources. When FPGAs are used as the primary platform in a digital design laboratory, increased flexibility and topical integration is provided to the instructor. Topics that have traditionally been taught in separate, independent laboratory assignments can be bridged together to form a cohesive series of laboratory projects based on a single problem scenario. This paper will present a series of laboratory exercises that center around a model train track with multiple tracks, trains, sensors, and switches. Keywords: Field–programmable gate array, FPGA, digital design laboratory. I