A comparison between two different FPGA-based topologies of first order sigma-delta modulator

Integrating sigma-delta modulator (SDM) in FPGA causes to have quantization noise inside interested bandwidth. This paper compares and analyzes between two possible FPGA-based SDM structures which are non-noise shaper SDM and noise-shaper SDM. The difference between these two structures is in the integrator block. All other SDM constitutive components are the same for both structures. First-order noise-shaper SDM with its maximum integration for FPGA implementation is reported. The advantages of noise-shaper SDM over non-noise shaper SDM are the elimination of input peak signal error as well as the increment of input voltage range. Moreover, higher suppression in signal harmonics results in better reconstruction of input signal at the output. However, the most important outcome is the improvement of quantization noise shaping out of the interested bandwidth which results higher SNR at the output

Sigma-delta analog to digital converter on field programmable gate array

Integrating analog to digital converter (ADC) in single system on chip (SoC) is a significant demand for portable electronic applications. Most of the input sources are in analog while the processing are in digital. ADC can be implemented in FPGA utilizing low voltage differential signaling (LVDS) available on the board. Sigmadelta ADC (SD ADC) is the best choice to be embedded in FPGA because it demands for less analog components. Integrating SD ADC in FPGA will cause to have quantization noise inside interested bandwidth which diminishes the effective number of bit (ENOB) and signal to noise and distortion (SINAD). In order to compensate the quantization noise, multi stages digital filter and high order FIR filter can be used. However, it occupies a considerable amount of logic elements (LEs) in FPGA that limits the space for main digital functions after ADC. Noise shaper sigma-delta modulator (SDM) in conjunction with hardware efficient digital filter (cascaded integrator comb, CIC) will provide not only less noise and less LE usage,but it also improves the ENOB and SINAD of the output digitized signal. The noise shaper SDM is implemented with its maximum integration. In general, the first order SD ADC consists of SD modulator (SDM), digital filter and decimation stage. Three architectures of 1st order SD ADC are implemented in FPGA in this work with different SDM and digital filter topologies but with the same complexity. The functionality of the SD ADC structure is written in verilog hardware description language (HDL). The evaluation is held in Altera Cyclone II FPGA chip on a Development and Education I (DE I) board. Comparing all the structures, it is found that noise shaper SDM with sinc filter order 2 gave the best result. The result of the 8-bit SD ADC achieves high SINAD of [45.14 dB – 39.57 dB] and ENOB of [7.21 –6.28] bits in operative frequency bandwidth of 10 kHz. This work improves the SINAD by approximately 8.3 dB, as well as improves the ENOB by 1.37 bits increase