Spiderweb Array: A Sparse Spin-Qubit Array

One of the main bottlenecks in the pursuit of a large-scale-chip-based quantum computer is the large number of control signals needed to operate qubit systems. As system sizes scale up, the number of terminals required to connect to off-chip control electronics quickly becomes unmanageable. Here, we discuss a quantum-dot spin-qubit architecture that integrates on-chip control electronics, allowing for a significant reduction in the number of signal connections at the chip boundary. By arranging the qubits in a two-dimensional array with about 12μm pitch, we create space to implement locally integrated sample-and-hold circuits. This allows us to offset the inhomogeneities in the potential landscape across the array and to globally share the majority of the control signals for qubit operations. We make use of advanced circuit modeling software to go beyond conceptual drawings of the component layout, to assess the feasibility of the scheme through a concrete floor plan, including estimates of footprints for quantum and classical electronics, as well as routing of signal lines across the chip using different interconnect layers. We make use of local demultiplexing circuits to achieve an efficient signal-connection scaling, leading to a Rent's exponent as low as p=0.43. Furthermore, we use available data from state-of-the-art spin qubit and microelectronics technology development, as well as circuit models and simulations, to estimate the operation frequencies and power consumption of a million-qubit array. This work presents a complementary approach to previously proposed architectures, focusing on a feasible scheme to integrating quantum and classical hardware, and identifying remaining challenges for achieving full fault-tolerant quantum computation. It thereby significantly closes the gap towards a fully CMOS-compatible quantum computer implementation. QuTechQCD/Vandersypen LabQuantum Circuit Architectures and TechnologyBUS/TNO STAFFQN/Veldhorst LabQuantum & Computer EngineeringQN/Vandersypen La

Spiderweb Array: A Sparse Spin-Qubit Array

One of the main bottlenecks in the pursuit of a large-scale-chip-based quantum computer is the large number of control signals needed to operate qubit systems. As system sizes scale up, the number of terminals required to connect to off-chip control electronics quickly becomes unmanageable. Here, we discuss a quantum-dot spin-qubit architecture that integrates on-chip control electronics, allowing for a significant reduction in the number of signal connections at the chip boundary. By arranging the qubits in a two-dimensional array with about 12μm pitch, we create space to implement locally integrated sample-and-hold circuits. This allows us to offset the inhomogeneities in the potential landscape across the array and to globally share the majority of the control signals for qubit operations. We make use of advanced circuit modeling software to go beyond conceptual drawings of the component layout, to assess the feasibility of the scheme through a concrete floor plan, including estimates of footprints for quantum and classical electronics, as well as routing of signal lines across the chip using different interconnect layers. We make use of local demultiplexing circuits to achieve an efficient signal-connection scaling, leading to a Rent's exponent as low as p=0.43. Furthermore, we use available data from state-of-the-art spin qubit and microelectronics technology development, as well as circuit models and simulations, to estimate the operation frequencies and power consumption of a million-qubit array. This work presents a complementary approach to previously proposed architectures, focusing on a feasible scheme to integrating quantum and classical hardware, and identifying remaining challenges for achieving full fault-tolerant quantum computation. It thereby significantly closes the gap towards a fully CMOS-compatible quantum computer implementation

Novel maximum likelihood approach for passive detection and localisation of multiple emitters

Abstract In this paper, a novel target acquisition and localisation algorithm (TALA) is introduced that offers a capability for detecting and localising multiple targets using the intermittent “signals-of-opportunity” (e.g. acoustic impulses or radio frequency transmissions) they generate. The TALA is a batch estimator that addresses the complex multi-sensor/multi-target data association problem in order to estimate the locations of an unknown number of targets. The TALA is unique in that it does not require measurements to be of a specific type, and can be implemented for systems composed of either homogeneous or heterogeneous sensors. The performance of the TALA is demonstrated in simulated scenarios with a network of 20 sensors and up to 10 targets. The sensors generate angle-of-arrival (AOA), time-of-arrival (TOA), or hybrid AOA/TOA measurements. It is shown that the TALA is able to successfully detect 83–99% of the targets, with a negligible number of false targets declared. Furthermore, the localisation errors of the TALA are typically within 10% of the errors generated by a “genie” algorithm that is given the correct measurement-to-target associations. The TALA also performs well in comparison with an optimistic Cramér-Rao lower bound, with typical differences in performance of 10–20%, and differences in performance of 40–50% in the most difficult scenarios considered. The computational expense of the TALA is also controllable, which allows the TALA to maintain computational feasibility even in the most challenging scenarios considered. This allows the approach to be implemented in time-critical scenarios, such as in the localisation of artillery firing events. It is concluded that the TALA provides a powerful situational awareness aid for passive surveillance operations