A method for the measurement of the turn-on condition in MOS transistors

Metal-oxide-silicon (MOS) integrated circuits usually consist of MOS transistors and interconnections. Both, interconnections and MOS transistors are built up of diffused regions in the bulk substrate and conductive strips (metal or polycrystalline silicon) on top of the oxide. For proper electrical operation the interconnection paths should not exhibit MOS transistor effects, i.e. should not induce inversion layers at the silicon-silicon dioxide interface. Furthermore from a designer's point of view it will be desired that some transistors operate in the saturated mode and others in the non-saturated mode. This implies that a method for the determination of the turn-on of channel conduction is highly desirable for designers of MOS integrated circuits. Using a straightforward definition of turn-on, a fast and simple measurement method will be presented for the determination of the relation between gate voltage and diffused region voltage for MOST structures in the turn-on condition

A CMOS class-AB transconductance amplifier for switched-capacitor applications

A CMOS operational transconductance amplifier (OTA) using a fully differential single-stage core OTA as the input stage and a differential to single current converter as the output stage, each biased at a separate current level, is presented. A large gain-bandwidth product (2.7 MHz) and a high slew-rate (5 V/μs) can be obtained by applying a large bias current to the core OTA. Due to the class-AB operation of the output stage, a high output impedance can be obtained by applying a small bias current to the output stage, resulting in a high DC-gain (61.6 dB). When the performance of this class-AB OTA is compared with that of basic single-stage OTAs it is found that the output impedance of the class-AB OTA is increased without limiting the bandwidth or slew-rat

Low-power low-voltage chopped transconductance amplifier for noise and offset reduction

This paper describes the principle and design of a CMOS low-power, low-voltage, chopped transconductance amplifier, for noise and offset reduction in mixed analogue digital applications. The operation is based on chopping and dynamic element matching, to reduce noise and offset, without excessive increase of the charge injection residual offset. Experimental results show residual offsets of less than 150µV at 100kHz chopping frequency, a signal to noise ratio of 95dB, in audio band, for 100KHz chopping and a THD of -89dB. The power consumption is 594µW

Charge loss experiments in surface channel CCD's explained by the McWhorter interface states model

On the basis of the McWhorter interface states model the CCD charge loss is derived as a function of bias charge, signal charge and channel width. As opposed to existing models, the charge loss is now attributed to interface states in the entire gate area, even for high bias charge levels. Experimental confirmation of the novel model is presented

Separation of random telegraph signals from 1/f noise in MOSFETs under constant and switched bias conditions

The low-frequency noise power spectrum of small dimension MOSFETs is dominated by Lorentzians arising from random telegraph signals (RTS). The low-frequency noise is observed to decrease when the devices are periodically switched 'off'. The technique of determining the statistical lifetimes and amplitudes of the RTS by fitting the signal level histogram of the time-domain record to two-Gaussian histograms has been reported in the literature. This procedure is then used for analysing the 'noisy' RTS along with the device background noise, which turned out to be 1/f noise. The 1/f noise of the device can then be separated from the RTS using this procedure. In this work, RTS observed in MOSFETs, under both constant and switched biased conditions, have been investigated in the time domain, Further, the 1/f noise in both the constant and the switched biased conditions is investigated